>
>Subject: Re: SIMM, Address Lines Order?
> From: Scott Stevens <chenmel at earthlink.net>
> Date: Mon, 26 Sep 2005 18:24:22 -0500
> To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org>
>
>On Mon, 26 Sep 2005 10:35:16 -0400
>Allison <ajp166 at bellatlantic.net> wrote:
>
>> Tim Olmstead wrote a Z80 Dram interfacing manual thats around the net
>> and cover simms as well as the ram on them. Very useful. I have an
>> electronic copy locally if needed.
>>
>
>The Z80 has DRAM refresh functionality built right into the processor,
>if I'm remembering right.
You remember right but there was a gotcha. the Z80 refresh was only 7bits
and about half the 64k drams requried a 256 (8bit) refresh. the solution
was with later parts you could do cas/ only refresh and that used the Drams
(later parts and those used for simms) internal counter for refresh address.
Allison
>
>Subject: Re: Odd floppy drives (Helitron)
> From: "John Allain" <allain at panix.com>
> Date: Sat, 24 Sep 2005 22:30:15 -0400
> To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org>
>
>> He claims that he was the inventor of the basic
>> floppy mechanism ... This was around 1980, maybe 1979.
>
>69 ~ 70?
>I mean, by 1980 floppies were down to 5.25" and the 8"
>had been out well over 5 years. Maybe the guy with the
>knob drive was lying even harder than you suspected.
>
>John A.
Definately older than 1974.
The oddest I'd seen was Ionovex The mech was about 8" high and about as wide
but the media was a web of mylar with oxide and the head spun under it with
a variable radius. Strange affair. I got to see it as bare drive but never
as part of a system.
Allison
>From: "Scott Stevens" <chenmel at earthlink.net>
>
>On Mon, 26 Sep 2005 10:35:16 -0400
>Allison <ajp166 at bellatlantic.net> wrote:
>
>> >
>> >Subject: Re: SIMM, Address Lines Order?
>> > From: woodelf <bfranchuk at jetnet.ab.ca>
>> > Date: Mon, 26 Sep 2005 08:18:24 -0600
>> > To: General Discussion: On-Topic and Off-Topic Posts
><cctalk at classiccmp.org>
>> >
>> >der Mouse wrote:
>> >>>When connecting DRAM chips to the pins of a SIMM (i.e. laying out
>the
>> >>>traces) does it matter if the order of the address and data lines
>is
>> >>>preserved? [...]
>> >>
>> >>
>> >> What about refreshes? (This is a question, not a challenge; I do
>not
>> >> know enough about how dynamic RAM refresh works to know whether
>this
>> >> really is relevant. But it seems to me that it might be.)
>> >>
>> >
>> >Just that all of them gets refeshed in the alloted time.
>> >Note they just have to be read for refesh. Still you better
>> >check the data sheets if you got them for the fine print.
>>
>> If your using cas\ only refresh then the data lines are not used
>> as that is done with internal refresh counter.
>>
>> Tim Olmstead wrote a Z80 Dram interfacing manual thats around the net
>> and cover simms as well as the ram on them. Very useful. I have an
>> electronic copy locally if needed.
>>
>
>The Z80 has DRAM refresh functionality built right into the processor,
>if I'm remembering right.
>
Hi
Only 128 cycle. Be careful. Some RAMs are 256 cycle.
Dwight
>
>Subject: Re: SIMM, Address Lines Order?
> From: woodelf <bfranchuk at jetnet.ab.ca>
> Date: Mon, 26 Sep 2005 08:18:24 -0600
> To: General Discussion: On-Topic and Off-Topic Posts <cctalk at classiccmp.org>
>
>der Mouse wrote:
>>>When connecting DRAM chips to the pins of a SIMM (i.e. laying out the
>>>traces) does it matter if the order of the address and data lines is
>>>preserved? [...]
>>
>>
>> What about refreshes? (This is a question, not a challenge; I do not
>> know enough about how dynamic RAM refresh works to know whether this
>> really is relevant. But it seems to me that it might be.)
>>
>
>Just that all of them gets refeshed in the alloted time.
>Note they just have to be read for refesh. Still you better
>check the data sheets if you got them for the fine print.
If your using cas\ only refresh then the data lines are not used
as that is done with internal refresh counter.
Tim Olmstead wrote a Z80 Dram interfacing manual thats around the net
and cover simms as well as the ram on them. Very useful. I have an
electronic copy locally if needed.
Allison
OK, what does a DEC H605E Motor Drive Amplifier go in?
It is a six by eight board with four TO-3 transistors, heatsinked, plus a
few diodes and stuff.
William Donzelli
aw288 at osfn.org
When connecting DRAM chips to the pins of a SIMM (i.e. laying out the
traces) does it matter if the order of the address and data lines is
preserved? In other words, does A0 on the SIMM need to connect to A0
on the chip, and A0 on all the other chips as well? These are old
DRAM, such as FPM or EDO, used in 30 pin SIMMs. Nothing new and
fancy like SDRAM.
I believe the answer is no. But I know from experience that there
are sometimes odd scenarios that are easily overlooked, so I figured
I'd access the shared experience and knowledge here.
It's a lot easier to layout the PCB for the SIMMs, if I don't
preserve order. And it shouldn't matter, because anything that gets
stored at address X should come back out on a read to address X.
The only circumstance I can think of that could cause a problem is if
the RAM has some kind of sequential read mode where consequeutive
addresses are expected. Reading the datasheet, I don't see a mode
like that. The closest thing is a burst mode where the Row address
stays constant and a series of Column addresses are supplied, but
that should work just fine, I think.
So, any gotchas to disordering the address and data pins between the
SIMM, and the chips and from chip to chip?
Jeff Walther
I do not hold these but I've been asked if I want them.
Allison
>I sent this earlier to arrl.org, but I thought I would also try here. These
>are free to the first taker, but that may be the rubbish man !
>Apollo 400
>Apollo 715s/50
>Apollo 715t/50
>(2) Apollo 715/64
>Apollo 400
>
>Subject: Re: difference between LSI-11 CPU's M7264 and M7270
> From: Pete Turnbull <pete at dunnington.plus.com>
> Date: Mon, 26 Sep 2005 21:52:59 +0100 (BST)
>Of course many of these are copies of each other, but I'm sure if there
>were an error, DEC would have corrected it at some time between 1975
>and 1983 :-)
>
;) my 81 and 83 copies do not agree with the 76/77 copy. considering its
was obtained internal to DEC it may have been a first printing. I had
to use my lsi-11 system service manual as the arbiter as its later than 83.
If I were actually working on the system I'd just pull the cage and look
before grabbing the book. Then again I do have a assortment of Qbus
and a few have non standard backplanes that were never supplied in
the boxes I have them in.
Allison
On Sep 26 2005, 13:34, Allison wrote:
> Pete Turnbull wrote:
> > No, that's not right. It's ordinary serpentine. I don't have one,
but
> > I just checked the Microcomputer Handbook myself, and it's
definitely
> > like this:
> >
> > A B C D
> > processor
> > option 2 option 1
> > option 3 option 4
> > option 6 option 5
> >
> > It's on page 6-3, and the expansion options, with the cable coming
from
> > where I've shown "option 6", are shown on 6-19. It's also shown in
the
> > same arrangement on page 426 of the Microcomputer Interfaces
Handbook.
> >
> Explain the drawings on pages 6-19 and 6-20 of the 76/77
microcomputer
> handbook.
The drawings on 6-19 and 6-20 in my copy show standard serpentine, as I
drew above, ie with the last option (or, in those drawings, the
terminator/cable connector) in the bottom left.
This also matches my handouts from the DEC QBus training course I went
on in the early 80s, the diagram on page 2-4 of the 1976 Microcomputer
Handbook, Fig.3-16 "Daisy-Chain Priority" on page 3-27 of the 1983
edition of the BA11-M Technical Manual, Fig.1-9 on page 1-12 of the
LSI-11 Processor Handbook, Fig.4-2 "H9270 Option Positions" on page 4-4
of the 1978-79 Memories And Peripherals Handbook, Fig.4 "BA11-M
Expansion Box Interconnections" and Fig.5 on pages 93 and 94 (chapter
on BA11-M) of the 1983-84 Microcomputer Interfaces Handbook, Fig.2
"H9270 Option Positions" on page 367 of the same 1983-84 handbook,
ditto pages 72, 73, and 426 of the 1980 edition.
Of course many of these are copies of each other, but I'm sure if there
were an error, DEC would have corrected it at some time between 1975
and 1983 :-)
--
Pete Peter Turnbull
Network Manager
University of York
Ok, back home, and thanks to all suggestions, I found the following.
Barely visible is the writing H9270, so that clears up what backplane
is installed in the card cage. The power supply is indeed an H780.
I have a copy of "microcomputer handbook" 1976-77, and on page 2-4
at the bottom is figure 2-2 which shows (literally, table and text):
A B C D
------------------+------------------
1 | position 1 | position 2 | <--- positions 1 & 2 are
------------------+------------------ normally used for
2 | position 4 | position 3 | the processor module
------------------+------------------ in single backplane
3 | position 5 | position 6 | systems and the first
------------------+------------------ backplane in multiple
4 | position 8 | position 7 | backplane systems
------------------+------------------
Anyway, I was enough assured to apply power. Double joy, because the
fans do not make an awful high pitched sound, just "normal" blowing,
and I got on the terminal the output
173002
@
So, that looks like one more system in my collection :-) Lucky for
me it is a small system. I need something more to make it usable.
The RXV11 from Pete Collum crossed my mind ...
thanks for all good info!
- Henk, PA8PDP.
