>
>Subject: Re: FPGA VAX update
> From: woodelf <bfranchuk at jetnet.ab.ca>
> Date: Wed, 02 Nov 2005 13:24:07 -0700
> To: General Discussion: On-Topic and Off-Topic Posts <cctalk at classiccmp.org>
>
>Allison wrote:
>
>>Ego a 16bit machine September 1985. There was another article whose
>>focus was microprogramming vs sequential machine control and that used
>>the TOY1 archetecture. There were others described in TCJ Dave Brooks
>>simplex III comes to mind. There are others.
>>
>>
>>
>Toy I had forgotton.
>Since TJC is now defunct are there any on-line copies of it I have read
>the simplex web site.
Dave Brooks has the simplex story on his site (along with the P112).
There is also a web ring for homebrew CPUs, quite a bit of diversity
out there but PDP-8 is common along with minimalist machines for teaching.
However the most interesting is the Block 1 AGC (apollo guidence computer).
Allison
Hi all,
I don't know why, but my mails seem to delay at least 30 hours before
they appear on the list. I have sent an update on my troubleshooting
findings and a reply on Julian's e-mail about the Flip Chips, *all*
yesterday (writing this e-mail Friday morning ...).
Anyway, here are my new findings, and conslusions.
On diagram KY-4, I checked the address decoder E34, and the 74154.
As expected, the outputs KY4 LD REG 0H and KY4 LD REG 1H are active
(otherwise keypad scanning and the display would not work at all).
The address decoder also puts out select signals to the RAM and
the 'KY ROM 2 EN L'. At first, I did not see any pulses on the output
'KY4 ROM 1 EN L', and I thought "AHA"! Too early, but that's OK!
I grabbed the 8008 code source listing and checked. ROM 2, E33/E39
on page KY-2 are almost continuously addressed, because the monitor
program loop sits in these 2 ROMs (address range 000-777 octal).
Checking the listing, I see that the first code in ROM 1, E3/E21,
is the processing of the LSR button, and the code comment actually
says "turn on SR DISP". When I press the LSR button, both ROM 1's
are addressed.
My conclusion is that all 4 ROMs are OK, as is the address decoder
(which is also a ROM) and the 74154 (all with the associated logic).
On page KY-1, the 8008 state output lines, S0, S1, and S2, go to
a 7442 decoder. The documentation explains the decoded states, and
mentions that pin 2 of the 7442 ('KY1 STOP L') is asserted when the
8008 crashes (in fact, when the 8008 executes a HALT instruction,
which is octal 0, or 1, or 377). When STOP L is activated, the 8008
will restart itself. I scoped pin 2, and can say that 'STOP L' is
never asserted.
That means that the 8008 is continuously executing its program,
without any restarts. The clock signal at TP1 is a nice square wave
with a duty cycle of approx 50%, cycle time a bit more than 1 uSec.
>From the above I conclude that more parts are functioning correctly:
- the 8008 CPU + clock and power-up/restart logic
- the transceivers E16/E17 that buffer the multiplexed addr/data bus
- the 2 RAMs (E11/E27)
- the 4 ROMs (E3/E21/E33/E39)
- the address latches (E5/E4) because they buffer the ROM addresses
- address decoder ROM (E34)
- "register" selector 74154 (E48)
It is time to find out why only the 3 lsb displays flicker brief
when I press a button, and why the msb 3 displays do not react at all.
I also saw that sometimes the RUN LED is turned on.
Pressing the CNTRL (only that button!) the BUS ERR LED goes on (???).
Normally CNTRL must be used in conjunction with another button ...
Pressing CLR makes BUS ERR turn off.
Also, I noted that at some point the display showed "666666", but I
can not change the value. For now, I am not too worried about this.
I contribute this behaviour to the less-than-perfect contacts, now
that the M7859 is on top op 2 dual width extender boards (so that I
can probe pins of the ICs on the M7859).
Again, any comments or hints are highly appreciated!
- Henk, PA8PDP.
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>
>Subject: Re: That darn Intel jingle...
> From: "Chuck Guzis" <cclist at sydex.com>
> Date: Thu, 03 Nov 2005 17:11:30 -0800
> To: cctalk at classiccmp.org
>
>On 11/3/2005 at 8:01 PM Allison wrote:
>
>>8274 is the intel branded NEC D7201, and it's not essentually a Z80 sio
>>it's IS a SIO save for it supports 8080/8085/8088 interrutpts instead.
>>Even the register addresses and functions are the same save those for
>>the interrupts.
>
>Someone once told me (could be urban legend) that the same guy designed
>both chips--once for Zilong and then for Intel..
>
>Cheers,
>Chuck
Definately urban legend. If only because it was licensed to Intel from
NEC who designed it. Early intel 8272s were old NEC mask. I even cleaved
an early Intel marked ceramic part for a customer to prove it. The design
came from NEC Japan.
Stuff you learn by being there.
Allison
>
>Subject: Re: That darn Intel jingle...
> From: "Chuck Guzis" <cclist at sydex.com>
> Date: Thu, 03 Nov 2005 15:32:44 -0800
> To: cctalk at classiccmp.org
>
>On 11/3/2005 at 6:22 PM ard at p850ug1.demon.co.uk wrote:
>
>>The worst, by far, has to tbe the 8255 parallel chip. That was clearly
>>designed by soembody who didn't think what he was doing. For those of you
>>who've not read the data sheets, any write to the mode control register
>>clears all output port lines to 0.
>
>For what it is and WHEN it was developed, the 8255 is a pretty good device.
> There are still new products made that use it (very popular in the data
>acquisition area). I can't think of any other single parallel interface
>chip from the 70's that's still puffing along.
Z80 PIO.
However the 8255 is of the 8080/8085/z80/ and general Intel lineup and
due to that also the most widely multiply sourced. It's ugly but what
comes in to do better?
>I wish the thing was faster. The NEC 82C55AC variant is good to 10 Mhz,
>but that's pretty slow when you're talking about a PCI bus.
D72055 the last version of the part hit 12mhz. If your going on PCI
why bother and just put a gate array to work.
>There are precious few of the really good peripheral chips from the early
>days of the microprocessor that are still as useful. The Signetics 2651
>USART, maybe?
Well there are plenty of 8251, 8253, 8259 around, then there are the 2681s
and (gag) 8250 series.
Not many but then what do you need after lots of ram?
Allison
>
>Subject: Re: That darn Intel jingle...
> From: "Chuck Guzis" <cclist at sydex.com>
> Date: Thu, 03 Nov 2005 16:17:54 -0800
> To: cctalk at classiccmp.org
>
>On 11/3/2005 at 6:45 PM Allison wrote:
>
>>Z80 PIO.
>
>16 measily bits of I/O in a 40 pin package. :( What a waste of real
>estate.
But long lived.
>>D72055 the last version of the part hit 12mhz. If your going on PCI
>>why bother and just put a gate array to work
>
>Mostly laziness. I could probably also just buy a PCI data acquisition
>board, if I didn't want Mode 2 I/O (which I do).
I used 8155s but then again I also use 8085s which work nicely with it.
>>Well there are plenty of 8251, 8253, 8259 around, then there are the 2681s
>>and (gag) 8250 series.
>
>Well, the 8259's a CPU support chip, and I tend to think of the
>8253/54/57/37 the same way.
the 53 (timer),54(Timer), 57(DMA) and 37(better DMA) are not strongly
related to any specific CPU and work fine with Z80, 808x even 8048.
>The 51's a peripheral chip that's had its share of warts, however.
8251 is wartly enough but ok. The Leading Edge Model D XT clone used
it rather than the icky 8250.
> The 8250 is a ridiculous National product that
>can't do sync in a single-channel 40 pin package yet. The Z80 SIO and the
>Intel 8274 are essentially the same chip that should have probably been
>made part of the PC instead of the 8250.
8274 is the intel branded NEC D7201, and it's not essentually a Z80 sio
it's IS a SIO save for it supports 8080/8085/8088 interrutpts instead.
Even the register addresses and functions are the same save those for
the interrupts.
>Speaking of which--I've got a bunch of Z80 DART chips. I've been told that
>these are really derated Z80 SIO chips. Will they do synchronous I/O or
>has that part been disabled? I can't find my databook for the things any
>more.
>
>Cheers,
>Chuck
>
DART is Async only, still a good part.
Allison
> If you ask me the real horror of parity memory is it only tells
> you disaster happend just as your about to crash.
And 1/9th of the time it's a false positive.
Lee.
..
___________________________________________________________
How much free photo storage do you get? Store your holiday
snaps for FREE with Yahoo! Photos http://uk.photos.yahoo.com
Folks,
While looking for the Lisa PASCAL workshop for one of my site visitors I
discovered the 7-disk floppy set for Lisa XENIX
Anybody want? It's only 1.2mb. I don't have the means of easily writing 400k
floppies so I'll not be putting it on my Lisa any time soon.....hmm...wait a
minute....I've just spotted a Mac Classic on the floor.....and an LCII.
*thinks*
Cheers
Adrian @ BinaryDinosaurs
Okay, so I FINALLY worked out my BA11-K power supply issues and got
everything sorted out and installed again.
However, I'm back to where I started when I got this thing (which I never
got past) - I turn it on, the display comes up at 173536. However, whenever
I try to EXAM anything, it displays 000000 and the BUS ERR light comes on.
I can clear, but I get that BUS ERR no matter what I do. I haven't got a
serial console connected to it yet - I got this info by going through the
11/34 diagnostics in the manual.
Here's my setup:
BA11-K box
DD11-PK backplane
UNIBUS layout:
A B C D E F
M8266 M8266 M8266 M8266 M8266 M8266 1
M8265 M8265 M8265 M8265 M8265 M8265 2
M9301 M9301 M7800 M7800 M7800 M7800 3
H222A H222A H222A H222A H222A H222A 4
blank blank blank GRANT blank blank 5
H222A H222A H222A H222A H222A H222A 6
blank blank blank GRANT blank blank 7
M7850 M7850 M7859 M7859 M7859 M7859 8
M9302 blank blank GRANT blank blank 9
I've tried switching some boards around, no help.
All grant cards are installed where you could read FLIP CHIP from the
processor side.
I have NO idea what's wrong. Is the memory possibly bad? That's the only
thing I could think of.
Any help, as always, would be much appreciated.
TIA
Julian
>
>Subject: Re: FPGA VAX update, now DIY TTL computers
> From: Sridhar Ayengar <ploopster at gmail.com>
> Date: Thu, 03 Nov 2005 11:04:58 -0500
> To: General Discussion: On-Topic and Off-Topic Posts <cctalk at classiccmp.org>
>
>woodelf wrote:
>> Chuck Guzis wrote:
>>
>>> Consider the very old Packard Bell PB250--22 bit words, fewer than 400
>>> transistors and 2500 diodes, 63 instructions. Power consumption about 40
>>> watts, exclusive of I/O:
>>>
>>> http://ed-thelen.org/comp-hist/BRL61-p.html
>>> The trick, of course, is to use bit-serial methods. It seems to me that
>>> one could greatly simplify construction of a homebrew machine that way.
>>> We're not doing this for speed, right?
>>>
>>>
>>>
>> That is interesting reading. Are there any of the large 48 bit
>> processors still around?
>> Also TTL and memory is easy to use in 4 bit sizes, a odd size like 18
>> bits is not so
>> easy to work with.
>
>How does parity memory work? Must one use the extra bit for parity or
>could one use it as a ninth data bit?
>
>Peace... Sridhar
Parity required an extra bit to stor the parity so that it could be compared
on read. That bit may or may not have been part of the data path logic.
Allison
