3 Nov
2005
3 Nov
'05
10:13 a.m.
Subject: Re: FPGA VAX update, now DIY TTL computers
From: Sridhar Ayengar <ploopster at gmail.com>
Date: Thu, 03 Nov 2005 11:04:58 -0500
To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>
woodelf wrote:
Parity required an extra bit to stor the parity so that it could be compared
on read. That bit may or may not have been part of the data path logic.
Allison
Chuck Guzis wrote:
How does parity memory work? Must one use the extra bit for parity or
could one use it as a ninth data bit?
Peace... Sridhar Consider the very old Packard Bell PB250--22 bit
words, fewer than 400
transistors and 2500 diodes, 63 instructions. Power consumption about 40
watts, exclusive of I/O:
http://ed-thelen.org/comp-hist/BRL61-p.html
The trick, of course, is to use bit-serial methods. It seems to me that
one could greatly simplify construction of a homebrew machine that way.
We're not doing this for speed, right?
That is interesting reading. Are there any of the large 48 bit
processors still around?
Also TTL and memory is easy to use in 4 bit sizes, a odd size like 18
bits is not so
easy to work with. 
3 Nov
3 Nov
11:08 a.m.
Allison wrote:
Parity required an extra bit to stor the parity so
that it could be
compared on read. That bit may or may not have been part of the data
path logic.
But on the memory chips, that bit must have been readable for the
system hardware to do its comparions. I guess that the memory could
send back a GO/NO_GO signal but supplying the parity bit must
be easier and cheaper?
There was a spate of "fake parity" memory around some time in
the 90s. Quite why it was cheaper to add a chip that always
supplied "correct" parity rather than simply using additional
memory was something that I never understood. But if you
end up with one these "fake parity" memories it may well
cause your 9-bit machine some issues!!
Antonio
--
Antonio carlini
arcarlini at iee.org
11:25 a.m.
Rumor has it that a.carlini at ntlworld.com may have mentioned these words:
There was a spate of "fake parity" memory
around some time in
the 90s. Quite why it was cheaper to add a chip that always
supplied "correct" parity rather than simply using additional
memory was something that I never understood.
Think of it this way:
Memory - lots of transistors per cell == $$
Fake Parity - only a few transistors[1] to fake it == less $$.
The fake parity chip was something like less than 1/10 the cost of a memory
chip, so if you could add (admittedly non-working) parity memory for a 1%
increase in cost compared to real parity at 12.5% increase in cost... yea,
my math ain't perfect, neither is my grammar - you get the picture. ;-)
That's why most Americans are happy with Butt^H^Hd Light.
:-/ [[Blech!]]
Laterz,
Roger "Life's too short to drink cheap beer" Merchberger
[1] relatively speaking, of course.
--
Roger "Merch" Merchberger | Anarchy doesn't scale well. -- Me
zmerch at 30below.com. |
SysAdmin, Iceberg Computers
11:29 a.m.
a.carlini at ntlworld.com wrote:
There was a spate of "fake parity" memory
around some time in
the 90s. Quite why it was cheaper to add a chip that always
supplied "correct" parity rather than simply using additional
memory was something that I never understood. But if you
end up with one these "fake parity" memories it may well
cause your 9-bit machine some issues!!
Well for my 9 bit machine, I am using 16k x 1 and 16k x 4 static ram
chips to give me
64kb of memory out of 256kb of total ram. As far as I know I the fake
parity chips
were dynamic ram. I hope to have 16k of ram for the OS and 48k for user
programs.
However the first goal is to finish the hardware design and debug it for
me.This is turning
into a wider 6800 style processer, but still a small system.
Antonio
1:26 p.m.
There was a spate of "fake parity" memory
around some time in the
90s. Quite why it was cheaper to add a chip that always supplied
"correct" parity rather than simply using additional memory was
something that I never understood.
Because fake parity needs just 2*lg(N)-1 XOR gates (N being the number
of data bits per word), one of them being NXOR if odd parity is used;
real parity needs 2^M memory cells (M being the number of address
lines). For any memory configuration that made it out of the lab, fake
parity is orders of magnitude less complicated a chip - and
correspondingly cheaper.
/~\ The ASCII der Mouse
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X Against HTML mouse at rodents.montreal.qc.ca
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2:31 p.m.
der Mouse wrote:
Because fake parity needs just 2*lg(N)-1 XOR gates (N
being the
number of data bits per word), one of them being NXOR if odd parity
is used; real parity needs 2^M memory cells (M being the number of
address lines). For any memory configuration that made it out of the
lab, fake parity is orders of magnitude less complicated a chip - and
correspondingly cheaper.
But the 9th memory chip already exists and costs thruppence
(with discounts for bulk) whereas a parity chip needed to
be designed and built and still come in cheaper. Maybe there
was one conveniently around (there would have to be an
implementation just to do the actual parity checking in the
system, but that could have been buried somewhere in a
PC chipset chip somewhere).
Obviously it must have been worth someone's while, I just
remember being a little surprised that this sort of chicanery
could be made to pay off (at least for a short while).
Antonio
--
Antonio carlini
arcarlini at iee.org
6768
days inactive
6768
days old
5 comments
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participants (5)
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ajp166＠bellatlantic.net -
arcarlini＠iee.org -
bfranchuk＠jetnet.ab.ca -
mouse＠Rodents.Montreal.QC.CA -
zmerch＠30below.com