Yes, here: http://bitsavers.trailing-edge.com/pdf/dec/pdp11/memory/MP00672_MS11L_engDr… There is also a technical manual adjacent, with circuit descriptions. I will scope this up tonight and take a look! --FritzM.

On 2019-Feb-06, at 5:11 PM, Fritz Mueller via cctalk wrote: So I could have saved myself some fun if I had read the manual rather than just looking at the schematic. Not that they're way out of whack, but the mild disparity between the manual's 14.5uS and my calculated 11.7uS is curious (the calculation being based on the schematic RC values and the 555 equations).

On 2019-Feb-06, at 5:29 PM, Paul Koning wrote: Checking further.. 4116 datasheet specs 2mS, my calcs give a refresh period of 1.5mS, the 14.5uS from the manual would give 1.86 mS, 7% shy of 2. The schematic specs 1% resistors, and the parts list does appear to spec a high-tolerance "1%200PPM" cap. Although there are the internal voltage divider Rs in the 555 which are also critical for the timing and everything is 40+ years old. Idle speculation at my distance, we'll see what Fritz observes. Could be other problems in the refresh circuitry too, like failed outputs from the row counter, etc.

On 2019-Feb-06, at 10:37 PM, Fritz Mueller via cctalk wrote: 15.2uS gives a 1.95mS refresh, so it's awfully close to the 2mS spec, but still within. The datasheet I was looking at doesn't seem to give any spec for tolerance on the refresh so one would guess there's a safety margin built into the 2mS spec. Seems a little less-likely to be the problem, given(?) as well that you have fairly consistent (is deterministic overstating it?) behaviour. If you wanted to test it by experiment, without having to remove the installed Rs, you could test-clip another R in parallel with the 38.4K, probably something around 200K, to shorten the 555 period.

On 2019-Feb-06, at 3:39 PM, Fritz Mueller wrote: Mixed up To: fields. The following was intended to go to the list and was originally sent a moment before I saw Fritz's message mentioning the 555: Ha!, simple free-running 555 oscillator generating the refresh cycles (pdf.pg27). I suspect there is a mistake in the schematic there: V-555 more likely connects on the other side of R4 (E5.4-C1-R4, rather than E5.7-R4-R5) to make it into the standard 555 astable circuit. Based on that, calculations indicate that the output from E5 (TP18) should be around 85 KHz, cycling 6.4 uS high, 5.3 uS low. So it's generating a refresh cycle every 11.8 uS. With 7 bits used from counter E43 (128 rows) for full refresh, that's a cell refresh every 1.5mS which (without having checked the 4116 specs) sounds sensible for a DRAM from that period. Note the 555 (E5) is running on +12 or +15V, with a R voltage divider on the output before driving into TTL.

On 02/06/2019 04:24 PM, Brent Hilpert via cctalk wrote: Hmm, yes, if the refresh is done by one-shots and RC timing, a failed cap could silently kill the refresh trigger. An easy way to check is put something in a few locations and halt the CPU for some time (seconds to minutes). If the content is now gone, then the refresh is very likely not being done. Jon