1 Sep
2006
1 Sep
'06
4:56 p.m.
I've got a DEC SC008 star coupler, complete with rack, doors, and
everything that I'm never going to use. There's no way I'm going to ship it
(it's a complete short corporate rack, after all!) so anybody who wants it
would have to live within driving distance of Milpitas CA.
I'd really like to trade it for an H967 "short" traditional rack. Note
that the 967 is neither the taller H960 traditional rack, nor is it the
shorter new "corporate" style rack - the 967 is about 50" tall (with
casters) and holds 24U. I'd be happy with just the bare rack; I don't need
doors or side panels.
H967s aren't that common, though, so it's a long shot that I'll find one.
Let me know if you're interested in the SC008, even if you don't have one.
Thanks,
Bob Armstrong
6 Sep
6 Sep
1:11 a.m.
New subject: PDP-8m Console Switch Problems
I've been working on an old PDP-8m and the last :-) problem I'm
having is with the front panel switches (LOAD ADDR to be specific).
I thought I'd throw this out to see if anyone else has run across
this particular issue.
Of the front panel switches, DEPOSIT, EXAM, CONT all work fine.
The CLEAR, EXTD ADDR LOAD, and LOAD ADDR switches are nonfunctional.
I have verified the switches themselves are OK (low resistance < 1ohm
in either of the two SPDT positions, high resistance otherwise).
What I see is strange behavior in the debounce circuit, and in fact
the debounce circuit itself is one I have never seen before (and IMHO
the designer should be hung by his entrails).
In ASCII art, here is a synopsis of the circuit:
+5V +5V 1/6*7404
| 1/4*74S175 | |\
/ +-----+-----+ | \ to
470 \ GND--| Dn Qn |------| >O-----9318
ohm / | | | / priority
\ GND--|>Clk QBn |O--+ |/ encoder
| | | |
+-------------o| MR~ | |
| +-----+-----+ |
| | |
__O ADDR GND |
O-/ LOAD |
| O------------------------------+
|
+----+
|
__O XTND
O-/ LOAD
| O---------->QBn...
|
+----+
...
|
__O
O-/ DEPOSIT
| O---------->QBn...
GND
The inactive position of each of the six SPDT switches is in the
'up' state, such that all the QBn~ outputs are left floating, and
the MR~ reset input to all the flops (two 74S175 devices total)
is pulled low to ground thru the switch tree.
If any switch is toggled to the active state, the MR~ chain to
ground is broken, and the MR~ to all the flops goes high. This
has been verified and works as expected. When the switch makes
the other contact, the QB~ output (yes, the output) is backdriven
hard to ground while the switch is active. Ostensibly the idea
(at least I think) is that when the QB~ is pulled low this will
force Q high, which output is then inverted and presented to
the active low input of an eight bit priority encoder. When the
switch is released, the MR~ chain is again made, and all the
flops are then reset. So it goes in theory.
Now I've found that of the 6 sections of two 74S175 devices in
use, three work (all on one device) and three don't (split across
the two devices). For all the sections, I see the correct H/L
levels being asserted on all the 74S175 pins, its just that for
3 of the six the Qn outputs are solid low, never toggling high
when the respective switch is made.
For what it's worth, the bottom three switches in the chain work
reliably (DEP, EXM, CONT), the top three don't (CLR, EXTD, ADDR).
I don't think is just a coincidence, but a symptom, but of what?
Switch resistance and/or capacitance is about all I can think of.
I've replaced the top 74S175 device (originally a Signetics 74S175
date code 1970) with a socket, and have tried other 74x175 parts
but none work at all (NAT 74LS175 1983, TI 74AS175 1986, SIG 74S175
1984, TI 74175 1974). Even on the bench in a proto board I can't
get any of these devices to behave like the original. Yanking the
QB~ output to hard ground does not force the Q output high. So
was DEC relying on the aberrant behavior of a 1970 Signetics 74S175?
I'm about ready to rip out the two bogus '175s and replace them with
some other logic (three '00s if I calculate correctly).
Anybody have any other ideas on what to look for or at?
Don North
AK6DN
1:57 a.m.
New subject: PDP-8m Console Switch Problems
-----Original Message-----
From: cctalk-bounces at classiccmp.org
[mailto:cctalk-bounces at classiccmp.org] On Behalf Of Don North
Sent: woensdag 6 september 2006 10:12
To: On-Topic and Off-Topic Posts
Cc: cctech at classiccmp.org
Subject: PDP-8m Console Switch Problems
[... snip ...]
(and IMHO the designer should be hung by his entrails).
Agreed!
[... snip more ...]
I'm about ready to rip out the two bogus '175s
and replace
them with some other logic (three '00s if I calculate correctly).
I can't be of much help, because shorting a TTL output to force
a transition in the inside logic of the D flipflop to flip the
other output, is not my cup of tea.
However, perhaps this will work. It keeps the 175, but you might
need some changes in the traces/wriring, Don.
+5V +5V +5V
| | |
| | |
|~| |~| |~|
| | | | | |
|_| |_| |_| 1/6*7404
| | | 1/4*74S175 |\
| | | +-----------+ | \ to
| | +---| Dn Qn |------| >O-----9318
| | | | | / priority
| +-----+----|>Clk | |/ encoder
| | | |
+----------------o| MR~ Qn* |o---
| | +-----------+
| |
__O ADDR |
O-/ LOAD |
| O------------+
| (active position)
GND
The switch is drawn in its rest position. The flipflop is held in
reset thru MR* at GND. The D input is already high. When you push
the switch, MR* goes high at a moment later CLK goes low. When you
release the switch Clk goes high again, and the flip flop loads
the D input to the output. A moment after that MR* goes low again
and resets the flip flop.
This is theory ... test in practice :-)
success, Henk
PA8PDP
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8:26 a.m.
New subject: PDP-8m Console Switch Problems
Hi Don,
On Wednesday 06 September 2006 01:11, Don North wrote:
--snip--
In ASCII art, here is a synopsis of the circuit:
+5V +5V 1/6*7404
| 1/4*74S175 | |\
/ +-----+-----+ | \ to
470 \ GND--| Dn Qn |------| >O-----9318
ohm / | | | / priority
\ GND--|>Clk QBn |O--+ |/ encoder
+-------------o| MR~ | |
| +-----+-----+ |
__O ADDR GND |
O-/ LOAD |
| O------------------------------+
+----+
__O XTND
O-/ LOAD
| O---------->QBn...
+----+
...
__O
O-/ DEPOSIT
| O---------->QBn...
GND
--snip--
Anybody have any other ideas on what to look for or
at?
The method of tying a switch (or OC pulldown) to the output of a FF in order
to "forcibly" switch it is not particularly uncommon. (If you think that's
bad, you ought to see some of the PDP-1 logic ;-)
At any rate, the circuit is described in detail in the PDP 8/E/F/M maintenance
manual Volume I on pages 3-108 and 3-109 - and IMHO - it's a good write-up.
I, too, had to hack my way though that circuitry to get my PDP-8/F working. I
had very similar symptoms to what you are experiencing (some control switches
working, some not) but the indications were quite different.
Here's a couple of suggestions:
1) Since the circuit, as designed, works perfectly for the several PDP-8/E/Fs
I've worked on (and thousands of others that were in production), I wouldn't
"redesign" it.
2) I'd check the inverters on the output of the 74175 to see if they are
pulling the FF the "other way".
3) If the inverters are O.K., I'd start tracing out the circuit to make sure
there's not a short and/or open between/in the related traces.
Cheers,
Lyle
--
Lyle Bickley
Bickley Consulting West Inc.
Mountain View, CA
http://bickleywest.com
"Black holes are where God is dividing by zero"
6682
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ak6dn＠mindspring.com -
bob＠jfcl.com -
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lbickley＠bickleywest.com