6 Sep
2006
6 Sep
'06
4:11 a.m.
I've been working on an old PDP-8m and the last :-) problem I'm
having is with the front panel switches (LOAD ADDR to be specific).
I thought I'd throw this out to see if anyone else has run across
this particular issue.
Of the front panel switches, DEPOSIT, EXAM, CONT all work fine.
The CLEAR, EXTD ADDR LOAD, and LOAD ADDR switches are nonfunctional.
I have verified the switches themselves are OK (low resistance < 1ohm
in either of the two SPDT positions, high resistance otherwise).
What I see is strange behavior in the debounce circuit, and in fact
the debounce circuit itself is one I have never seen before (and IMHO
the designer should be hung by his entrails).
In ASCII art, here is a synopsis of the circuit:
+5V +5V 1/6*7404
| 1/4*74S175 | |\
/ +-----+-----+ | \ to
470 \ GND--| Dn Qn |------| >O-----9318
ohm / | | | / priority
\ GND--|>Clk QBn |O--+ |/ encoder
| | | |
+-------------o| MR~ | |
| +-----+-----+ |
| | |
__O ADDR GND |
O-/ LOAD |
| O------------------------------+
|
+----+
|
__O XTND
O-/ LOAD
| O---------->QBn...
|
+----+
...
|
__O
O-/ DEPOSIT
| O---------->QBn...
GND
The inactive position of each of the six SPDT switches is in the
'up' state, such that all the QBn~ outputs are left floating, and
the MR~ reset input to all the flops (two 74S175 devices total)
is pulled low to ground thru the switch tree.
If any switch is toggled to the active state, the MR~ chain to
ground is broken, and the MR~ to all the flops goes high. This
has been verified and works as expected. When the switch makes
the other contact, the QB~ output (yes, the output) is backdriven
hard to ground while the switch is active. Ostensibly the idea
(at least I think) is that when the QB~ is pulled low this will
force Q high, which output is then inverted and presented to
the active low input of an eight bit priority encoder. When the
switch is released, the MR~ chain is again made, and all the
flops are then reset. So it goes in theory.
Now I've found that of the 6 sections of two 74S175 devices in
use, three work (all on one device) and three don't (split across
the two devices). For all the sections, I see the correct H/L
levels being asserted on all the 74S175 pins, its just that for
3 of the six the Qn outputs are solid low, never toggling high
when the respective switch is made.
For what it's worth, the bottom three switches in the chain work
reliably (DEP, EXM, CONT), the top three don't (CLR, EXTD, ADDR).
I don't think is just a coincidence, but a symptom, but of what?
Switch resistance and/or capacitance is about all I can think of.
I've replaced the top 74S175 device (originally a Signetics 74S175
date code 1970) with a socket, and have tried other 74x175 parts
but none work at all (NAT 74LS175 1983, TI 74AS175 1986, SIG 74S175
1984, TI 74175 1974). Even on the bench in a proto board I can't
get any of these devices to behave like the original. Yanking the
QB~ output to hard ground does not force the Q output high. So
was DEC relying on the aberrant behavior of a 1970 Signetics 74S175?
I'm about ready to rip out the two bogus '175s and replace them with
some other logic (three '00s if I calculate correctly).
Anybody have any other ideas on what to look for or at?
Don North
AK6DN