Steven Hirsch wrote: Thanks! I added it with the comment "discussion" since you have to join the group to have access to the files. The only other CoCo project I had found seems dead. Though I never had this computer, I did build one with the same chipset and so have some fondness for it. But I now think using those chips was a mistake, since for $40 in TTLs (the cost of the 6847 and the 6883) I could have gotten a much nicer v?deo. -- Jecel

On 12/11/11 9:24 PM, jim s wrote: A cross-assembler exists, fwiw: http://www.dbit.com/pub/linux/macro11/ --T

...except that you have to (a) be willing to run either Windows or Linux, (b) run on their choice of hardware, and either (c1) set up a very heavily firewalled sacrificial system or (c2) trust the security of your system to code they aren't even willing to let you look at. I'm not willing to do (c2) at all, and not willing to do either (a) or (c1) unless I'm getting paid a fair bit to do so ((b) might join (a) and (c1), if their required hardware is something I don't have, though that's highly unlikely). I'm much less concerned about tools than I am about documentation on the hardware's interface, on what the bits in the blob thrown at the hardware mean (and how to thrown them at it, though that part is much more likely to be documented). I would probably find open-source tools useful mainly as hardware documentation, though if they are properly designed I might be able to pull off their UI and stick on something I find usable. I'd love to get into FPGA hacking. But not nearly enough so to tolerate something as abusive towards their users as "you have to run our closed-source code". :-? /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

On 11/12/2011 9:30 PM, Dave McGuire wrote: Works for Altera, too. I do it on Windows with cygwin. 'make generate' and then load the programming file when done. I know I could probably setup the makefile to do the steps only as needed, but I have not really found it to be worthwhile (since most changes are to the verilog source, which requires a complete rebuild anyway). DESIGN=DE0_PDP8 TOOLS=/cygdrive/c/tools/altera/10.1sp1/quartus/bin generate:: $(TOOLS)/quartus_map $(DESIGN) --write_settings_files=off $(TOOLS)/quartus_fit $(DESIGN) --write_settings_files=off --seed=1 $(TOOLS)/quartus_asm $(DESIGN) --write_settings_files=off $(TOOLS)/quartus_sta $(DESIGN) $(TOOLS)/quartus_sta -t generate_timing.tcl $(DESIGN) 10 $(TOOLS)/quartus_eda $(DESIGN) --write_settings_files=off -c $(DESIGN) $(TOOLS)/quartus_cpf -c $(DESIGN).cof clean:: -rm -f $(DESIGN).*.rpt $(DESIGN).*.summary $(DESIGN).*.smsg $(DESIGN).map $(DESIGN)_assignment_defaults.qdf TQ_*.rpt PLL*.txt -rm -f $(DESIGN).done $(DESIGN).map $(DESIGN).pof $(DESIGN).sof $(DESIGN).jic $(DESIGN).pin $(DESIGN).jdi $(DESIGN).qws $(DESIGN).*.ddb -rm -rf db incremental_db simulation # the end

As far as I know there is no complete open FPGA (or even CPLD). By 'completely open' I mean that there is sufficient docuemtation available (without an NDA) to go from a design (be that as a schematic, a wirelist, VHDL, whatever) to the necessary data to program into the chip, and be able to actually program that data into the chip. This is in contract to microcontrollers where in many cases the machine code (and special-purpose registers, I/O ports, etc) is fully documented, as is the way to get the object code into the chip (e.g. by ysing a JTAG interface). It is quite possible to write an aassembler (or programmer) and program loader for such devices. In the case of the FPGAs I've looked at, the actual way to get the data into the chip is docuemtned, but what all the bits mean is not. designed with FPGas as part of a job, and didn't enjoy it much. It is very different from designing logic cirucitry the old-fashioned way for a start. For a one-off design, where size is no real issue, I much prefer to grab a handful of TTL pacakges and start soldering. -tony

And I'd avoid those like the plague, I dislike stray cpaacitance and unreliable contacts. I increased my designing speed no end when I started soldering things up from the start. I am not convinced. A PDP11/05 is just 2 hex cards. Perhaps a couple of hundred packages. That's easily doable (as in I've built things of that sort of complexity). -tony

I do get moderately annoyed with people who tell me what I should and should not enjoy :-). If you are paying me to design soemthing, then I'll use very difrenet desing criteria and devices to what I'll do if I am doing it for myself. In the latter case maximising my pleasure comes a long way up the list. I do not enjoy (really) doing anything much at a computer screen. I don';t like programing, I don't like entering VHDL, I don't like scheamtic capture. I am happiest using a pen and paper and a soldering iron. As I said, it's for myself, I do it becuase I enjoy it, so I use the methods I enjoy. In what way have the deives improved? I totally disagree with the first (having built things with a few hundred pacakges (at least). And as for the second, OK, I'll grab some ECL (I#'ve hand-wired ECL circuits that go at sevearl hundred MHz with no problems). Quite apart from the fact that as I said at the start 'for me as a hobbyist'. I may not want ot make large or high-speed designs (and what appears to require high speed logic may not if you actually think about the problem). -tony

On Sun, 13 Nov 2011, Tony Duell wrote: While this is true of current FPGAs, I dont think this is completely true, the Xilinx XC6200 and perhaps some other manufacturers chips have this information available. Also there are some brave souls poking about at open source tools as well, for example: www.milkymist.org/fpgatools Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your (")_(") signature to help him gain world domination.

David Riley wrote: Xilinx XC2064, introduced in 1985.

Zitat von Eric Smith <eric at brouhaha.com>: IIRC, there were called FPGA much later. Introduction was as "LCA"

I can confirm that the term "FPGA" was used early on and that Xilinx's "LCA" never caught on. Back in 1986 I had a nice chat with someone at the company (I think it was the president, but am not sure) who was very excited that there were people way down in Brazil trying to use their product. It was a lot of fun to use XACT on a CGA 8086 PC to set each logic block individually and route each wire through all the intermediate switches. I couldn't get the design to be fast enough, unfortunately, and had to use TTLs and PALs instead. The XC6200 was a favorite among the academic people (I was just offered two boards with this chip last week) but was never used in any product and was dropped. It had come from outside Xilinx and had never really meshed well with the rest of that company's products: http://www.algotronix.com/people/tom/album.html The reconfigurability came back in a more limited form in the Virtex architecture (and so in Spartan II and later as well) and though the detailed information about the bit files were never released, there was a library called JBits which was made available to selected groups which did give you full control over the configuration bits. This was not updated to handle newer chip families as these became available and eventually JBits vanished. Atmel had two families of FPGAs, the AT40K and the AT6000. They are both tiny and limited by today's standards, but teh AT6000 (if I remember correctly) did have its configuration bits fully documented and for a while I considered using it in my projects for this reason. The VPR academic FPGA tools could be used with JBits to do the whole job on old Virtex chips. http://www.eecg.toronto.edu/vpr/ There was a project to figure out the configuration bits for Virtex chips which was part of a larger project to build a PDP-10 with FPGAs. I don't think either was finished: http://neil.franklin.ch/Projects/VirtexTools/ Here is a series of papers about more recent efforts to generate configuration bits without using the vendor tools: Roman Lysecky, Frank Vahid, and Sheldon X.-D. Tan. 2004. Dynamic FPGA routing for just-in-time FPGA compilation. In Proceedings of the 41st annual Design Automation Conference (DAC '04). ACM, New York, NY, USA, 954-959. http://dl.acm.org/citation.cfm?id=996819&preflayout=flat Etienne Bergeron, Marc Feeley, and Jean Pierre David. Toward on-chip JIT synthesis on Xilinx VirtexII-Pro FPGAs. In International IEEE Northeast Workshop on Circuits and Systems (NEWCAS'07), pages 642-645, August 2007 http://www.iro.umontreal.ca/~feeley/papers/BergeronFeeleyDavidNEWCAS07.p df Etienne Bergeron, Marc Feeley, and Jean-Pierre David. Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs. In International Conference on Compiler Construction (CC'08), volume 4959 of Lecture Notes in Computer Science, pages 178-192, March 2008 http://www.iro.umontreal.ca/~feeley/papers/BergeronFeeleyDavidCC08.pdf Etienne Bergeron, Louis-David Perron, Marc Feeley, and Jean Pierre David. Logarithmic-Time FPGA bitstream analysis: A step towards JIT hardware compilation. ACM Transactions on Reconfigurable Technology and Systems, Vol 4, No 2, Article 12 (May 2011), 27 pages http://dl.acm.org/citation.cfm?id=1968502.1968503&preflayout=flat -- Jecel

On 11/15/2011 02:45 PM, Tony Duell wrote: "Knowledge is power", and tie-wearing thieves who otherwise would have no use at all make themselves powerful by hoarding knowledge. Keeping secrets, in everything from technical documentation to employee salaries, makes otherwise-unimportant people feel important. -Dave -- Dave McGuire New Kensington, PA

OF course. I was not implying that there can't be (or shoudln't be) useful original reserch which involves FPGA configuration. I am sure there can be new algorithms for laying them out, there is much that can be done on self-modifying hardware, and so on. My point is that _that's_ the research. Having to start by rediscovering known information that 'we won't tell you' is not research. It's a waste of intellegent people's minds. -tony

FWIW, I love simulation with FPGAs. It usually reveals my beginner mistakes, and is a pretty powerful tool to help test your design. While I haven't done enough to demonstrate it, there are differences between simulation and real hardware. Altera's synthesis tools are pretty nice and do things like identifying metastability problems, and telling you approximately how long until data becomes stable. I was using someone else's design that had an issue, and it reported 17ns of metastability. For a quick fix, I added a couple 10ns wait-states, and the design worked immediately. I understand the right fixes are dual clocked FIFOs, dual flip-flop synchronizers, etc. While I create my designs with pen and paper first, the simulation can show step by step, clock for clock, what's happening, what state I'm currently in, and for what reason it transitioned. Because I'm working with two different systems, a 5v TTL system, and a 3.3v LVTTL system (the FPGA), I wasn't able to directly connect them, but I wanted some verification that my hardware I described is working as it should. I attached my logic analyzer to the 5v system and captured data. Then, after exporting that data and massaging it a little, was able to import that into my simulation and watch how my hardware (would have) processed those set of signals. Very cool -- there was no easy way to test this otherwise. Plus you can test things like boundary conditions that shouldn't ever show up in real life --- to see if your error handling works as it should. On a side note, I like using FPGA boards over just wiring up some chips together. I can access hundreds of open source modules, modules that ship from the vendor, macros, primitives, libraries, and so on. I couldn't imagine what your parts library would have to look like in order to accomplish the same thing with physical parts. Plus, it comes down to speed. Using gate-level verilog, I can plunk down a couple gates, wire in a switch, wire up an LED, whatever in a matter of seconds. Compile, push the configuration, and play with it. Probably before your soldering iron heats up completely. (har har) And then wack the HDL, start something different, use the onboard memory blocks, PLLs, etc. I really enjoy this method of design for my hobby. Keith

On 11/15/2011 9:00 PM, ben wrote: True, but your compilation tools _will_ tell you that. It will tell you exactly how many of which type of resources are required, and since you can target different platforms (heck, different vendors if you were careful with your HDL) without even owning/having the hardware. Keith

Mouse wrote: [...] I'm not sure what kind of problem you're trying to describe here. Can you give an example? I've found that Verilog can be used to model any digital logic design I can think of, including a lot of things that can't be done in an FPGA, and that the synthesizer does a good job of alerting me to that kind of issue. VHDL is more expressive in some ways than Verilog, but cannot represent transmission gates, while Verilog can. However, FPGAs generally don't have transmission gates exposed to the user, so it isn't a problem for FPGA design. As far as I know, there is no reasonable logic design using transmission gates that can't be restructured to use something else instead. Transmission gates are really a hardware optimization, and not part of pure digital design.

Mouse wrote: VHDL lets you design such things, as does System Verilog. The FPGA synthesis tools will certainly tell you that it can't fit it into an FPGA. That said, it is possible to implement some types of A/D and D/A converters in an FPGA with only a few external components. There are application notes about that. Obviously the capabilities are very limited compared to normal ADC and DAC parts, but there are times when it is nevertheless quite useful.

I think you're missing the point. The problems start when part of the design will not (and isn't suppoed to) fit in any FPGA (or even any FPGA supported by the tools you're using). Perhaps you want to have a significant amount of memory. Perhaps so much that you cna't get an FGPA that will hold the logic _and the memory_. No problem in the real hardware, you conenct a memory chip to the FPGA. But a lot of FPGA_specific simulators can't handle that. It gets worse if the external memory is somplex to talk to, like many forms of DRAM. Trying to simulte a DRAM _inside an FPGA_ and have it fial i nthe right ways if the timing is wrong, just so you can simulate the DRAM controller you were designing in the first place is fraught with problems. Then there's the time you wnat to link your PFGA circuit to some external devies. Suppose you're designing a disk controller for a PDP11, anf you want it to use DMA and interrupys. I hardlly think you should try ot desing a UUnibus or Qbvus arbitor in the simulator just so you can test your deisng. And yet many, many, simulators can't handle tie idea of 'If you get this signal form my circuit, then assert this one 100ns later, then wait for my cirucit to assert this...). Or if you have an external device that accepts and produces a bitstream of some kind. Simulating that is always 'fun'. Somebody already mentioned genrating video signals in an FGPA. I don';t know about you, but I can't look at the waveforms going into the DACs (which is waht a ismulator is most likely to show) and see what the image will look like. Of course anythign weith ADCs or DACs is goign to be a problem. -tony

On 15 Nov 2011 at 20:40, Keith Monahan wrote: This and Tony's comment about using discrete logic rather than FPGA points up an interesting, but important, limitation of FPGAs (and CPLDs): they're clocked designs. While Tony can use his 7400-series logic to implement an asynchronous design, almost all FPGA implementations must have a clock of some sort. Not every design employing logic is a CPU and not all employ clocked logic. Someone who wants to substitute, say, a CPLD for a bunch of unclocked TTL is going to have to come up with a clock--and then determine how that will affect function. Achronix is the only vendor that I can recall offhand even discussing aysnchronous FPGAs--and it's not even clear to me if they're still offering them. Simulation must be a nightmare. --Chuck

Oh! That's a very important thing I hadn't known before. I'd been assuming an FPGA was, well, a big chipful of gates which you wired up however you wanted, and which then behaved like, well, the bunch of gates you've wired them up as; whether any of the signals those gates processed could be considered a clock would be irrelevant. I'm glad to have this mental model corrected _before_ I did anything based on it. That's a pretty crippling limitation for many purposes. Quite. I have a boardful of TTL which I designed and built to allow a parallel port to control (via relays, driven off discrete transistors controlled by logic levels) a bunch of mains outlets. There are a few signals which could sort of be seen as clocks - for example, one of them drives the clock input to a shift register - but no global clock that applies to the whole circuit. Would this be unrepresentable in an FPGA - or, rather, would it have to be redesigned to operate with a global clock to be representable in an FPGA? You make it sound like it. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

On 11/16/2011 2:00 PM, David Riley wrote: For some of the stuff that I do, I have to deal with multiple external asynchronous events and signals. Almost all of my designs are synchronous (usually with a module here or there that is purely combinatorial) and so you normally bring your asynchronous signals into your sync clock domain so that you can deal with it/process it/connect it to other modules, and so forth. My clock is normally much faster on the sync side than the async side, so having enough time to properly receive/sample the signal is easy. When you have multiple signals, it's just a matter of having separate processes(hardware, really) that deal with each signal independently. My designs are mostly finite state machines, because this makes the most sense to me, and I find that I can implement just about anything using one of them. The async signal causes a move from one state to the next, and then I react accordingly. When I've got to react to that async signal and immediately notify another external device, my clock is running fast enough, that the propagation delay through my logic is pretty tight. How long depends on the logic required, but again, since the sync clock is much faster --- it normally doesn't matter. You know, since both Altera's and Xilinx's tools are free --- one can download their multi-platform tools, code up some VHDL/Verilog/RTL/whatever and then simulate it using their included free simulators. Some of the timing analysis stuff is pretty neat to look at too. A lot of the descriptions of tools and simulations breaking down don't show up in normal hobby use. While it's not a fuzzy feeling knowing that the simulators/synthesizers aren't perfect, they are pretty damn good, and work absolutely fine for most small->medium sized projects. I'm still in the process of building my "things to avoid problem list", but there are common rules of thumb that if you follow, you'll likely go down a good path. Expecting these tools to somehow work magic and be 100% bug free is an unrealistic expectation and most people who expect this are drastically underestimating the complexity of tools involved. Modelsim for simulation and synplify pro for synthesis seem to be popular commercial standards. A limited Modelsim is included with Altera software, where Xilinx includes their iSim which isn't horrible. Altera's synthesizer seems to be better (properly inferring the hardware be a religious war I don't want to start. :) Keith P.S. vi rocks.

On 16/11/11 3:30 PM, Mouse wrote: Well said. And those of us who use expensive, proprietary software can easily feel victimised by it. (In my case, in a previous career, Adobe.) The "support" which is supposedly the privilege of paying through the nose and enduring lock-in - frequently just isn't really there. When was the last time a Windows user followed a bug through Microsoft's support system? Mostly they get endured and worked around. That's just things get done, in Proprietary Land... unless, I suppose, you are Fortune 100 and can use a red telephone. --T

On 11/16/2011 10:24 PM, Mouse wrote: I'm right there with you on that. Vendor support is nearly always a joke. It will never be half as good as an experienced engineer with access to the source code. Sun is particularly bad about this...I can't count the number of things I've taught Sun employees about Sun computers and OSs. -Dave -- Dave McGuire New Kensington, PA

On 17 November 2011 03:24, Mouse <mouse at rodents-montreal.org> wrote: I suppose it depends on your level of expertise. When I ran a DEC-based server network in the early 1990s, with fairly minimal knowledge of VMS except as a user, I found DEC support /excellent/ on a number of occasions. At that time, the fact that the call made its own way through callcentres around the world when I pulled an all-nighter was very impressive: whoever I spoke to, from India to Australia, knew the whole history and could hand-hold me through the next step. Best IT support I've ever had, in fact. Compare that to the bad joke that is vendor support in the PC industry, where the only thing they can really do right, if you've paid enough, is come round, swap out the affected device and replace it with a new one. This is why virtualisation and so on is getting so big, indirectly. There are few really clueful people in industry IT any more. The answers to most problems are: * If it's hardware, power-cycle it. If that doesn't work, replace it. * If it's software, wipe it & reinstall. So being able to migrate system images to heterogenous hardware, and just restore new blank system images with a click, are /massively/ useful tools. Overall, oh hell yes. Which is why it's annoying that one of the business arguments /against/ FOSS is that either there is no support or that it's really expensive. Free community support is generally more use than the professional paid-for stuff from the vendors, IMHO. -- Liam Proven ? Info & profile: http://www.google.com/profiles/lproven Email: lproven at cix.co.uk ? GMail/GoogleTalk/Orkut: lproven at gmail.com Tel: +44 20-8685-0498 ? Cell: +44 7939-087884 ? Fax: + 44 870-9151419 AIM/Yahoo/Skype: liamproven ? MSN: lproven at hotmail.com ? ICQ: 73187508

On 17/11/11 1:08 PM, David Riley wrote: We built an AMC card using (among other things) a Freescale MPC8378 (PowerPC microcontroller) on board that, at least for the first batch, had a few bizarre problems running at the promised 800 MHz. ... saying anything other than "well, you're probably not terminating it right, go re-spin your board", they just stopped responding to us. Shortly thereafter, supplies of the 800MHz speed grade dried up for a few months; after shipments resumed, the problem was fixed, so I guess we found a process/QA control problem for them? Th lack of communication was just infuriating, though. Could the litigation culture be part of why corporations are unable to be transparent about, or acknowledge, defects? --Toby > - Dave

THis matches my experiences too. I have never received useful techncial support from any computer company on either hardware or software. I've sent e-mail to the support address of several large software companies and never got a reply. I've sent letters to large computer comanies and had them ignored. Conversely, I've sent e-mail to the authors of open-source stuff -- who I fully realais are udner no obligation to help me at all -- and received useful infroamtion the next day. The reason I prefer open-couce software is not ideological, it's practical. If I have the source code even I (not a good programmer) can make an attempt to get it working properly. -tony

On 18/11/11 2:07 PM, Jochen Kunz wrote: TeX is only bug-free in the limiting case. --T

Is it? It is possible to write spaghetti code in any language. It is also possible to write clean, abstracted, even object-oriented code in any language. In each case, some languages make it easier than others. Web does not offer much help for abstractions, objects, interfaces, etc - but if anyone is capable of creating clean code in the absence of language assist, it would be Donald Knuth. I haven't studied the implementation enough to know whether there is any kind of abstraction or interfacing or whatnot going on there. I've done those things myself in C - which offers slightly more language assist for them, but I haven't always used it - but, even when I have, it isn't always obvious to someone reading the code but not going to the trouble to really understand it. So, unless someone who has thoroughly grokked the code says so, I see no particular reason to think TeX doesn't have that sort of clean design lurking in the implementation. Of course, that may have happened. But I don't see reason to think so in what you wrote. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

In article <4EC7E21F.9030005 at telegraphics.com.au>, Toby Thain <toby at telegraphics.com.au> writes: I know. OOP has been around as long as Simula IIRC 1968. Encapsulation and abstraction have been around for just as long if not longer. They aren't recent idioms. That's because practically noone can understand it besides Knuth, which is why noone has been changing it. Software that doesn't change doesn't have bugs introduced into it. Yes. *barf*. Yet here we are about 30 years after the fact and only an incredibly tiny portion (vanishingly small, I'd say) of existing software has adopted these "outsanding" methods. I'd say the wisdom of crowds has pretty much ruled this a failure. -- "The Direct3D Graphics Pipeline" -- DirectX 9 version available for download <http://legalizeadulthood.wordpress.com/the-direct3d-graphics-pipeline/> Legalize Adulthood! <http://legalizeadulthood.wordpress.com>

On 19/11/11 3:32 PM, Richard wrote: Yes, and what I said is also correct. The point is that they weren't commonly applied circa TeX's birth. (And nor does Knuth seem particularly seduced by them since.) Maybe that is true, but it's not because it's not thoroughly documented in prose... I said those *two books* are outstanding expository pieces of work, but of course there are other examples of literate programs as well. Literate programming didn't captivate the mainstream. But you know what? That's a pretty poor yardstick of quality. --Toby

On 19/11/11 6:00 PM, William Donzelli wrote: Amazing. Well, I guess everything turns to shit in the end. I don't even *like* CMR. Nice try for an amateur type designer, but I think its day is completely done. --Toby

Yes, and that is what, 1% of all academic publications? Maybe 0.1%, for stuff that Word can not handle? "Standard" is a funny word. -- Will

Correct, but Word can do most things quite adequately. What it can not do, academic writers can often "fake" (sort of like the old days where handwritten symbols were used), or they can use TeX. It appears that these days TeX is actually only used as a very last resort (or by diehards). In any case, TeX ceased to be the academic standard quite a lot of years ago. The academics I know seem to have rejoiced when PC/Mac word processors finally could do most of what they wanted, and they could go tell TeX to go take a walk in the woods. -- Will

On 20/11/11 2:55 AM, Dave McGuire wrote: Quite so: Not very many of those bug cheques were issued or cashed... http://www.flickr.com/photos/qu1j0t3/6373292909/in/photostream --T

On 20 November 2011 15:48, Tony Duell <ard at p850ug1.demon.co.uk> wrote: I have not following this thread closely but this caught my eye. In support of the answer, I note that LaTeX source is the preferred submission format for every math, computer science, physics, and chemistry journal that I know of. It is also extensively used by publishing houses such as Springer, CUP, and OUP. I cannot speak for humanities.

In article <CANij+ddU5AF8xWqHH+snPG8eFkHtaqVTUc-byXK+U9+erpVfqw at mail.gmail.com>, William Donzelli <wdonzelli at gmail.com> writes: As of about 2000, Addison-Wesley editors didn't even known what TeX was, much less have a process for working with an author using TeX. I was told that I'd have to handle *all* typesetting and formatting issues myself. -- "The Direct3D Graphics Pipeline" -- DirectX 9 version available for download <http://legalizeadulthood.wordpress.com/the-direct3d-graphics-pipeline/> Legalize Adulthood! <http://legalizeadulthood.wordpress.com>

On Nov 20, 2011, at 9:34 PM, William Donzelli <wdonzelli at gmail.com> wrote: Pandering to the least common denominator is common on our society. There are lots of Harbor Freight stores, but very few Starrett stores. Does that mean Harbor Freight sells better tools? -Dave -- Dave McGuire New Kensington, PA

I think if I ever found one (or a Moore & Wright store, which would be the approximate equivalent over here), my bank manager would be after my blood... -tony

You cna. of course, put various interpretations on these statements, but the very fact that they mention TeX and LaTeX implies to me that there are plenty of academics out there using said text formatter. -tony

It was thus said that the Great Tony Duell once stated: I've read up on literate programming (I even own a copy of "Literate Programming" by Knuth) but even so, I never liked the idea all that much, because it seems even *more* work than regular programming. For instance, I have a program I wrote between 1999 and 2001 that I still use to this day [1] and in that time, I merged what used to be two programs into one, replaced the IO system twice (I'm now on the third iteration) and just this month I replaced the configuration code [2]. Had this been a literate program meant that not only would I have changed about half the code, but half the verbiage would have had to change as well. At work, I deal with just a small portion of a project that involves at least half a dozen programs. One program (which doesn't actually do all that much) is 131,000 lines of code [3]. And since I've been on board (about a year) there have been at least two major architectural changes because of "issues" not forseen [4]. As it was, we barely finished on time [5]; having to rewrite sections of a "book" would have been dropped as soon as we missed the first milestone (given the push we were on to finish). Heck, just look at the difference between Linux 1.0 and 3.0. Imagine if that was done via literate programming, and how much work it would take to keep the verbiage up to date. Literate programming is just too much work. -spc (And frankly, after seeing some of the "documentation" we produced at work [6], literate programming would still be a failure) [1] http://boston.conman.org/about/technical.html [2] I replaced the configuration file, which was basically an RFC-822 format (since I had to parse RFC-822 style lines anyway) with Lua. The file looks much nicer, I can have real comments; I was able to remove a bunch of code that was replaced with several Lua modules so over all, I think it was a win. [3] Most of the code is a webserver to control the program, and another large portion is code to talk IS-41 over SS7. [4] One issue---one vendor's SMS stack took too long (on the order of half a minute or more) for what we needed to do. So out went the SMS and in went a hack^H^H^H^Hcustom protocol to implement the functionality. Another issue---one vendor's hardware didn't do what they claimed it could do, so we had to "fix" that by implementing what the hardware didn't do. And it goes on ... [5] Amazingly, we did finish on time. That's because we kept pushing back as much as possible. [6] Skipping the 1,000+ pages of non-documentation that makes up the SS7 stack, our own documentation is rather ... lack luster ... in spots. So much so that I've felt I've had to reverse engineer some of our own protocols we devised, and that's from looking at the soure code!

It was thus said that the Great Toby Thain once stated: My point is that software changes. Maybe, like one of the cases at work, what we thought would work (using SMS) didn't. That whole section of the code (and if it was a literate program, a whole section? Chapter?) was scrapped and a whole new mechanism put into place. That wasn't a case of "no time to do it right, but time to do it over" (to quote a future email) but a case of "even the vendor didn't know how their own SMS system worked" (or maybe didn't inform us---I'm not sure as I wasn't there for those meetings). TeX hasn't changed. Once written, the only changes have been the (very) occasional error. It wasn't an entire section scrapped (that we know of) because of a change in requirements. And yes, the project I've been working on is working; it's now in production and frankly, no bugs have been found---or rather, yes, bugs *have* been found, but on the vendor's network that were never documented nor mentioned to us, and thus, we had to work around those particular issues. Should we use literate programming? Frankly, we have some great programmers; what we don't have are great writers. That may be asking too much. -spc (Also, the intended audience for our work is ourselves (right now, five programmers total) and we don't license or give out the code. Too small an audience to write a series of novels, frankly ... )

It was thus said that the Great Mouse once stated: Have you tried writing a novel? Even writing 50,000 fictional words is tough (ba dum dum!). About the only time I've had that problem is when I modified sendmail.cf. Otherwise, I don't really recall a time when I've gone back to code I wrote years later and had trouble following it. Heck, I'm looking at some code I stopped working on in 1999 and I'm not having any problems with it. Amusement at what's there (hmm ... I must have started working on some persitent objects ... interesting) yes, amusement at how my coding style has changed since then, yes. Difficulty reading my own code? Not really (heck, just last year I was able to improve the speed of a 6,000 line program (is that all that is? Wow!) I last worked on in 1995, and the only documentation *is* the code). And there are those that ignore comments in the code as they might not bear any relationship to the code what-so-ever. I try to maintain comments, but even so, there are times when the comments drift out of sequence with the code (heh---I just modified some comments in another personal project that referenced code that's been removed for six years!) -spc (So, how many literate programs have you written? 8-P

On 21/11/11 1:03 AM, Sean Conner wrote: It is not clear how that suddenly implies that programmers need not write *about* their code. Au contraire, I would argue that it puts even *more* pressure on explanations and design documents. It went through one total rewrite (just like the modern systems you describe). Where did you write down all the information about those bugs and the workarounds, or are you carrying it in your head? The skills are not so widely separated. The great computer scientists (whatever one's opinion of their programs) have, by and large, been great writers*. And, to restate the case we have been making, the ability to write clearly is not necessarily a dispensable part of the job (and moreso, if a good part of the job is necessarily going to be to educate co-workers?). If you still doubt the Siamese connection between the ability to write well and the ability to code well, then please read The Elements of Programming Style before we continue this discussion. --T * - List on request. ? - http://www.reddit.com/r/programming/comments/l32qk/if_only_we_all_had_cowor…

On 21 Nov 2011 at 10:11, Jason McBrien wrote: I'll say only this--it depends upon how much code you write every day and how long it's been since you've seen it--and how memorable the project itself is. After about 20 years, I forget what I've written, and often, even that I've written it. Good commentary (not the line-by-line drivel, but block comments obeying the reporter's axion "Say what you're going to do, say what you're doing, then say what you've done") has saved my bacon countless times. --Chuck

On 21 Nov 2011 at 11:06, Brian Wheeler wrote: Heh. I vividly recall a fellow who proudly pointed out to me that every line of his code had a comment. Unfortunately, most were like: BX5 X1*X3 LOGICAL AND X1, X3 TO X5 Reading thousands of lines of drivel like this is insulting and indicates a lack of appropriate focus. On the other hand, a tight loop, with instruction timings written out as comments is quite informative. One more observation. I've read a lot of other people's code in my lifetime and one thing that stands out in sharp contrast from the run- of-the-mill awuful stuff is that the narrative commentary to good, inspired code is always well-formed, grammatically correct and often witty. Consider the fellow who's devised his own allocation algorithms using a Fibonacci series introducing his narrative with "Lieber Leser". Or the fellow who, in his buffer-management scheme makes reference to "guru beads". Or the database author who talks about quipus. When the same fellow was writing proposal text, he was equally engaging. And it's something that causes me a bit of despair when reading the 'Net-engendered 133T-text of young programmers. Now, get off my lawn... --Chuck

----- Original Message ----- From: "Chuck Guzis" <cclist at sydex.com> To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org> Sent: Monday, November 21, 2011 6:27 PM Subject: Re: Literate programming is too much work! - Re: TeX - Knuth - Software quality - Re: Bug-Free Software, I agree. There's nothing like skimming through source code and finding comments that reference a TV programme (or something else popular) from the time the code was written, especially if it's funny. On a relevant note, last week I added code to my first amiga demo (that I hope to release next month) that added double-buffering for a particular screen (the onscreen object would flicker every few seconds without it). One of the parts to the double-buffering referenced a label called ".not_logical_jim" (clearly a Star Trek reference, incase someone here doesn't get it). Regards, Andrew B aliensrcooluk at yahoo.co.uk

On 21 Nov 2011 at 15:23, Vincent Slyngstad wrote: Guru beads are, if memory serves, the perfect example of a ring of linked buffers. They're used as an aid for meditation or in counting aid when chanting (surely you remember Arthur C. Clarke's "The 9 Billion Names of God"--a 1950s SF story involving computers and religion.) Unlike a rosary, they have no beginning or end--you just keep reusing the beads. A similar idea is in the "Towers of Hanoi" story used by the authors of the SNOBOL4 book to illustrate recursion. You also have to understand that the GB example was written in the 70's by an ex-IBMer who lived with a band of gypsies in the Santa Cruz mountains. He'd come down to the valley to grab some work when his woman spent all of his money. He played a mean gypsy guitar and was vicious at p?tanque. West coast computing was far more colorful back then. Personally, I enjoy reading things that try to educate me--it keeps me from getting bored and piques my curiosity. But if you're not curious by nature, I can see where it might be tiresome. Coding is more than writing instructions--it's about communication. Some people will dedicate many lines of commentary explaining how a particularly complex piece of code operates, using any literary device to aid in understanding. I admire those who put in enough thought to take the time to write such stuff. --Chuck

On 22 Nov 2011 at 7:21, Vincent Slyngstad wrote: Maybe it's a cultural thing. If you've spent your life writing and maintaining applications, you probably don't have much of a sense of humor plowing through hundreds of thousands of lines of COBOL.. On the other hand, if you've spent your time writing systems code (drivers, operating systems, compilers, etc.), the view is a little different, I think. It could also be the times. When I started out, nobody had a degree in computer science--the discipline simply didn't exist. Nobody got into computer programming for the money and backgrounds were widely varied, so there was a lot of cross-pollination. I could not imagine, for the life of me, what starting out today would be like, with standardized everything, developing web applications, universities serving as trade schools for the profession. A bureaucrat's dream, it would seem. If I'd started today, I'd probably be a plumber. --Chuck

From: "Chuck Guzis"; Tuesday, November 22, 2011 9:08 AM I'm a kernel and driver guy myself, but the culture where I worked was not exactly laid back. From: "Toby Thain"; Tuesday, November 22, 2011 4:55 PM OK, I must have missed something. I thought I was commenting on a remark about a story about Guru Beads by an ex-IBMer who lived with gypsies in the mountains. Did his story have to do with complex numbers? It is this annoyance that I was originally trying to get at. It should be possible to stick to the cultural context that is likely to be shared with whoever has to fix the code later. I was arguing that it was helpful to do so, and leave the broadening experiences for another time. Vince

On 22/11/11 10:21 AM, Vincent Slyngstad wrote: It was a lecture on *complex numbers*. If you want to criticise the didactic style, go ahead; but instead, you wrote: 'there is a time and place for such stuff ... it's *not* in the middle of trying to understand and debug someone else's code' Did you not consider that the code in question might have involved complex numbers? Why assume it was an irrelevant digression? It could well be helpful for debugging or just understanding how the following code works. Um, touch?. And half the world wouldn't bother and would go ahead with the usual "what happens if I change *that*" haphazard fiddling. --T

It can, certainly. But it can also, at least in my experience, be anything from pure amusement (of both authors and readers) to citing a good analogy to the author's mental model, which can help immensely by aligning the reader's mental model with the author's. While of course I don't have enough information to do more than take stabs in the dark, I'd tentatively guess that "Lieber Leser" is at least partly a play on "Liber Abaci", falling into the "amusement" category (and relatively harmless if the reader doesn't get it), while the "guru beads" example may be an instance of the "analogy" case. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

It was thus said that the Great Chuck Guzis once stated: I don't add that many comments to my own code. But when I do, it tends to be stuff like: /*------------------------------------------------------------------------ ; Per http://www.cons.org/cracauer/sigint.html, the only proper way to ; exit a program that has received a SIGINT (or SIGQUIT) is to actually ; use the default action of SIGINT (or SIGQUIT) so that the calling ; program can detect that the child process (in this case, us) actually ; received a signal. So that's why we set the default handler for SIGINT ; and kill ourselves, since the only way we get here is via SIGINT (or ; possibly SIGQUIT if/when I add logic for that). ;------------------------------------------------------------------------*/ set_signal_handler(SIGINT,SIG_DFL); kill(getpid(),SIGINT); return EXIT_SUCCESS; /* keep this around to silence the compilers */ } or /*------------------------------------------------------------------------ ; check for origin field. We only look for IPv4/IPv6 literal addresses as ; that's the only reliable way to actually transmit such information (and ; parse it as intended per RFC3164). Thus, this code will fail if a ; hostname is sent, but it would also fail if the program name with an ; embedded space but no host is sent. ; ; I suppose I could check to see if the first white-space delimited field ; *only* contains alphanumberics, but then it could fail on a message that ; is sent that contains neither a host nor a program (which is possible). ; ; Pick your poison ... this works for me ;-------------------------------------------------------------------------*/ The other trick (I think) is picking good names that reflect what the function/subroutine is doing. I hope that a function named "GlobalsInit()" does indicate what it's doing. -spc (Another question about literate programming---what can I assume the intended audience to be? A fellow programmer at the same level as I? An intern? A C*O that's never programmed before?)

On Nov 21, 2011, at 5:51 PM, Andrew Burton wrote: Certainly when I'm annotating previously unknown assembly (particularly if it's a disassembly for which there are no comments or other semantic data to begin with), I tend to annotate EVERY line unless it does something stupidly obvious (like return, or a really obvious add right after a load, etc.) because I know I can't juggle all the register semantics around in my head while I'm still discovering them. In higher-level code, this is totally dumb: a++; // add one to a Whereas the following is helpful: *dst++ = *src++; // Copy a word of src to dst while incrementing both because, as mentioned, you're doing something "clever" that might not be immediately apparent to people (we discourage people who are just starting C from doing things like that exact example because until they've had more time to get used to it, they usually assume it means (*src)++ instead of *(src++) and re-use it the wrong way in their own code). Or, of course, if you've been intentionally obtuse about your variable names (chances are you should never REALLY have a variable named "a" unless there's a very good reason to do so), you might need to explain what "a" is when you increment it. Or, if it's a pointer to a struct, it's a good time to point out that you're incrementing the pointer by one struct stride, not one byte. It's a matter of whether the semantics are obvious, but I've found everyone has different metrics for that. - Dave

Sure, but incl d4 ; increment d4 is pointless even then. What helps under those circumstances - and, I would hope, what you do - is incl d4 ; increment array index or incl d4 ; increment count of...whatevers-they-are or incl d4 ; compensate for extra decrement inside loop or some such. ...then, unless you're writing for the IOCCC or some such, you've got bad code there, in at least that respect. Of course, one person's "intentionally obtuse" is another's "why bother, it's a temporary for all of ten lines of code" or even "what do you mean obtuse, it's perfectly clear". NODE *sort_nodes(NODE *list) { NODE *a; NODE *b; NODE *t; NODE **tp; if (!list || !list->link) return(list); a = 0; b = 0; while (list) { t = list; list = list->link; t->link = a; a = b; b = t; } sort_nodes(a); sort_nodes(b): ...(merge step omitted)... } I am unconvinced this is either a bad use of the names "a" and "b" or a case where there's "a very good reason" to use them (x and y, or s1 and s2, or any of many other choices, would be equally good). /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

In article <31E3916E-4E97-4A16-83C8-D1A6C4DC0E66 at gmail.com>, David Riley <fraveydank at gmail.com> writes: srsly? This is such a common C idiom, that I'd think anyone who feels this needs a comment shouldn't be using the language. -- "The Direct3D Graphics Pipeline" -- DirectX 9 version available for download <http://legalizeadulthood.wordpress.com/the-direct3d-graphics-pipeline/> Legalize Adulthood! <http://legalizeadulthood.wordpress.com>

On Nov 22, 2011, at 12:59 PM, Richard wrote: The point is that code I write often gets read by people who *don't* know C/C++ that well, but still feel the need to point out that it's "mysterious" in design reviews. Yes, that happens. Yes, we all have dumb customers/students sometimes. I prefer to forestall the idiotic review notes instead, because it's bad for business when I want to strangle customers. :-) I should also point out that it's a common C/C++ idiom for people who didn't grow up in a world where everything is a library. One might argue that people who don't know C/C++ well enough to understand the order of operations should probably learn a bit more before passing comment on someone else's work, but that's not the world we live in. - Dave

Someone wrote: *dst++ = *src++; // Copy a word of src to dst while incrementing both If I were looking at the code, I'd wonder why a memory move intrinsic wasn't used (memcpy/memmove) and would have appreciated commentary as to why it wasn't done. --Chuck

On 21/11/11 10:11 AM, Jason McBrien wrote: Not everyone agrees with this (e.g. Charles Simonyi*; even prodigies grow old). Code is *not*, on the whole, self-documenting - at least as it is written these days. And even if a single method is "obvious" (let's say it's short and sweet, 5 lines), where is the rationale for the design of the 900 classes that it nestles in? Does anyone document and write manuals for huge class hierarchies? Or does everyone just learn them the slow and painful way by having to maintain them day by day after the original programmers have left? "Do the simplest thing that could possibly work" doesn't mean "incorrect or badly". "Readable terseness" is very much undermined by the majority of popular mainstream languages. No proper macros; no pattern matching; etc, etc... They do run the spectrum from unhelpful to awful. --Toby * - http://www.hackerne.ws/item?id=560185

In article <BEB54E1E-9E0B-4054-A387-09C98454758B at gmail.com>, David Riley <fraveydank at gmail.com> writes: srsly? A PRODIGY? What crack have you been smoking? The guy was just another programmer, no better or worse than any other good programmer, who happened to be lucky enough to work at MSFT at the time when it could still make you a millionaire. -- "The Direct3D Graphics Pipeline" -- DirectX 9 version available for download <http://legalizeadulthood.wordpress.com/the-direct3d-graphics-pipeline/> Legalize Adulthood! <http://legalizeadulthood.wordpress.com>

On 11/22/11 10:05 AM, Richard wrote: He was working at PARC on Bravo-X and was courted by MSFT to develop WSIWIG word processing. He had a history with Lampson/Thacker et. al. back to the Berkeley/BCC days. You don't stay with that crew based on just luck. I'm kind of 'meh' on the early MSFT word processing products though.

On 22/11/11 2:08 PM, Richard wrote: I agree, but my point wasn't about Simonyi. It was about "prodigies" and people who feel their ability to read and write code is prodigious (for now...) Most Valley wealthy were simply in the right place at the right time; I think that's fairly self evident by now. --T

In article <4ECC2E2F.9060205 at brouhaha.com>, Eric Smith <eric at brouhaha.com> writes: I've read his original essay. It's still a shitty suggestion. -- "The Direct3D Graphics Pipeline" -- DirectX 9 version available for download <http://legalizeadulthood.wordpress.com/the-direct3d-graphics-pipeline/> Legalize Adulthood! <http://legalizeadulthood.wordpress.com>

Jason McBrien wrote: You must have a much better memory than most people. My experience, which matches that of every programmer I've spoken to about this, is that any code I wrote but last looked more than three years ago takes very nearly as much effort to understand as code of comparable quality by another author but which I've never seen before. That means that I find it worthwhile to document code well even if I think that the only audience for that documentation is my future self.

On Nov 22, 2011, at 7:56 PM, Toby Thain wrote: Well. Some pilots with excessive self-confidence don't use the checklists. They don't do that for long, though. - Dave

On 23/11/2011, at 7:51 AM, Eric Smith wrote: I've got code sitting on a shelf in my study that I wrote nearly 40 years ago. Just for interest's sake I thought I'd see if I could understand it - the answer is no, mainly as I can't really read PDP-10 assembler any more :-( I looked at some slightly later stuff (probably 35 years old) written in BCPL - I can read and understand it but don't know why I wrote it that way. I guess I've learnt something about algorithms in the intervening time! Huw Davies | e-mail: Huw.Davies at kerberos.davies.net.au Melbourne | "If soccer was meant to be played in the Australia | air, the sky would be painted green"

On Wed, Nov 23, 2011 at 23:44, Ethan Dicks <ethan.dicks at gmail.com> wrote: I dug up the oldest source I could find - it's probably the first FORTRAN program I wrote, from the early eighties. It's not a big program, it's for reading CP/M floppies on a minicomputer. There aren't many comments, but those that are there are important. I'm glad they're there. Commenting everything would have been totally overkill though, the code is easy to understand because the few comments are in the right place. Without them it would have been more work to understand the code. I'm pretty happy with what I'm seeing there. There seems to be about 10 to 15 lines of code per comment line. What's important is that the comments describe non-obvious things (if you only have the source and not, e.g. for this program, the documentation for the CP/M filesystem): IF (USER .NE. 229) THEN ;% -- 229 = E5 hex (non-existent entry) WRITE (1,11)USER, NAME, TYP, EXTENT, RECUSED ENDIF -Tor

From: Charlie Carothers Sent: Tuesday, November 22, 2011 11:18 PM ...and we come full circle. *That* was Knuth's point in creating Literate Programming. Just for the record, I made changes to TeX in the late 1990s to allow the use of larger fonts on the TOPS-20 operating system (which had been restricted to 128-character fonts by the usual use of 7-bit ASCII in text files). No bugs were introduced, and the sources in web were very good guides to the necessary changes. Neither tangle nor weave was unhappy with my changes. Rich Alderson Vintage Computing Sr. Server Engineer Vulcan, Inc. 505 5th Avenue S, Suite 900 Seattle, WA 98104 mailto:RichA at vulcan.com mailto:RichA at LivingComputerMuseum.org http://www.LivingComputerMuseum.org/

I find that doubtful; if so, he botched it far worse than I would have thought anyone of his skill and knowledge could. Web code - or, at least, what web code I've seen - is definitely divided into `code' and `comments'. (Web does a better job encouraging the programmer to keep the comments next to the code than many languages, but it's a long way I thought "the code _is_ the comment" was (much of) the point of COBOL, actually. It came closer than anything else I've seen, at any rate. It failed badly, not at "the code is the comment" per se but at the implied "the code doesn't need any additional comments", largely because to the extent that the code is the comment, the comment just echos the code. At the very best, that documents what and how; it cannot say why, and it cannot say what or how at any level other than the detailed one the code is written at. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

On 24/11/11 5:17 PM, Richard wrote: Apart from those who write crystalline pearls of clarity which work forever and never need to be touched again, the vast bulk of code spends most of its life in maintenance, and that rarely by the people who wrote it. (Hmmmm and have you tested that your code is "readable and understandable" to those who come later? Do they agree? What about the rationales for methods that simply aren't visible in the code?) If you don't comment it, do you at least document it? Doxygen/Javadoc/whatever would be better than nothing, to maintainers. Apart from the apparently controversial commenting "question", "The Elements of Programming Style" (op. cit.) deals thoroughly with issues of readability and comprehension in any language. --T

It was thus said that the Great Toby Thain once stated: I'm in the QA department, where I get to break the code our company writes (documentation of the actual spec is done in another department). But I did see reference to it in the revision log (we use SVN). In fact, I found it easier to track the code through the revision logs than the actual source code or documentation itself ("Oh, I see M added a new bit field to this structure, I best update the testing tool to support that"). So, how many people here have done any literate programming? -spc (Doesn't seem like many ... )

On 19/11/11 1:01 AM, Richard wrote: TL;DR: Literate programming is a failure because people are too lazy to read. --Toby

On 11/19/2011 03:33 PM, Richard wrote: Wow, such a well-articulated, and dare I say "literate" argument! -- Dave McGuire New Kensington, PA

It didn't But a one-word expletive with no justification is not useful IMHO. -tony

On 19/11/11 4:02 PM, Dave McGuire wrote: And their internals are practically *never* as thoroughly described in English as TeX and METAFONT are. And how many large object oriented systems have exponential bug bounties? Or could ever afford one? --Toby

On 11/19/2011 01:54 AM, Mouse wrote: "Program testing can be used to show the presence of bugs, but never to show their absence!" -Edsger Dijkstra -Dave -- Dave McGuire New Kensington, PA

On 11/16/11 6:55 PM, Eric Smith wrote: Is there anything higher-level/better for describing an cross-domain signal beyond specifying that it go through a dual-rank synchronizer?

David Riley wrote: This can sometimes be observed with off-the-shelf chips. For instance, suppose you have a 6502 system with an input port that simply gates unsynchronized input data to the bus using a tristate buffer. If you do an LDA from that port, and the port data changes violating the input setup time, you can get a situation where the loaded accumulator value has the MSB set, but the N flag is not set, or vice versa. Eric

I wrote: Al Kossow wrote: I don't know about "better", but a key observation is that if you are transferring an n-bit data word between two clock domains, and use full handshaking (request/acknowledge) between the domains, and guarantee that the data from the source clock domain meets the setup time of the destination clock domain, then you only need the dual-rank synchronizers for the handshake signals and not the data. The synchronization in that case can be further simplified, i.e., you could use Rob Weinstein's "flancter" circuit: http://www.floobydust.com/flancter/Flancter_App_Note.pdf In many cases people use FIFOs for passing data between clock domains. It is *very* tricky to design your own asynchronous FIFO correctly, so it is often a good idea to use a FIFO macro supplied by your FPGA/CPLD vendor or EDA tools vendor. In fact, it is so tricky that even the vendors don't always get it right; Xilinx had some pretty serious errata for the hard FIFO logic they provided with their blockrams in some FPGA families. What I've done when I don't need pipelining is to build a one-word FIFO by using a single register and a flancter. Eric

Al Kossow wrote: Yes, that's quite important, and although the application note mentions it, it doesn't show it in most of the diagrams. The author really should have called more attention to it. My VHDL version has two outputs, which are the output of the XOR synchronized to each of the clock domains. I did something that many people consider to be a no-no. I did the dual-rank synchronization with the first FF clocked by the inverted clock, to reduce the latency. The reason people say that's a no-no is that it doesn't do as good a job at reducing the probability of metastability. However, the probability of metastability with a clock of frequency f with opposite-phase FFs is exactly the same as the probability with conventional same-phase FFs at a frequency of 2f (provided that the FF characteristics are otherwise identical), so if you do analysis for 2f and get acceptable results, you can use frequency f with opposite phases. Eric

Am 18.11.2011 02:26, schrieb David Riley: Couldn't have been said better! In VHDL I mix signal and variable assignments in processes. I've been told *NEVER* to do that because it leads to unpredictable results - wrong, you just have to understand what's going on. Then it's perfectly save to mix variable and signal assignments. :-) Philipp

On 17 Nov 2011 at 16:29, Keith Monahan wrote: Written by some character named "Mike Stein". That wouldn't happen to be our own Mike Stein, would it? I remember reading the article--it comes from a time when EDN (and Electronic Design) still had good design columns. But both rags were a lot thicker then--now I think the advertising circular from the local dollar store has more pages... --Chuck

Ah, so the actual crippled piece is in that damn binary blob the vendor requires we use rather than documenting their configuration data. Another reason to dislike having to use their tools: the hardware can do things their tools have trouble with. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

On 11/16/2011 1:15 PM, Chuck Guzis wrote: Chuck: This really isn't true at all. While you are right that most designs are synchronous, there's no limitation or requirement for them to be so. You can do combinatorial logic all day without a clock. module AOI (input A, B, C, D, output F); assign F = ~((A & B) | (C & D)); endmodule is an example. module MUX2 (input SEL, A, B, output F); input SEL, A, B; output F; INV G1 (SEL, SELB); AOI G2 (SELB, A, SEL, B, FB); INV G3 (.A(FB), .F(F)); endmodule I've also simulated these, and it appears to work fine. Maybe in larger more complex designs, there's problems with simulations --- others here will have to testify to that. Am I missing something here? Why doesn't combinatorial logic designed in an FPGA count as a clockless design? Thanks Keith

On Nov 16, 2011, at 3:47 PM, Chuck Guzis wrote: Well, yeah, they'll complain, but that doesn't mean they won't build it. They're just confused because for the most part, they're built to expect synchronous designs and figure you're doing something wrong if they can't figure out a clock (and, honestly, for 99% of the designs out there, they're right; most people who are new to FPGAs don't understand what they're doing and develop things wrong and end up leaving out the clock or similar). The CPLD tools tend not to be as bitchy about it, mostly because registers are relatively scarce in CPLDs and so the converse is true; if you're using lots and lots of clocked registers, you're probably not using the right device for the job. My biggest pet peeve about FPGA design tools is the warnings they put out. You generally can't tell it "hey, this module is parameterized and generic so in this instance I'm not using this output", so anything you make properly generically will end up burying the real, important warnings in a sea of noise. You can't even use vendor IP (I'm especially thinking of memory controllers) without generating over 100 warnings, which drives me NUTS. I don't like combing through my synthesis report to see which of 800 messages is important. - Dave

On 11/16/2011 4:47 PM, David Riley wrote: Dave, You wouldn't happen to be talking about Xilinx's memory controller, would you? I get a ton of warnings. And it's surprising when they design both the controller and synthesizer. Altera's IDE has a way of suppressing "similar" warnings, or suppressing warnings that contain text. It's not ideal, obviously, better not to have the warnings --- but at least you can hide the false warnings so that the real ones are more visible. Keith

On 11/16/2011 11:31 PM, Dave McGuire wrote: In this particular case, Xilinx gives you a memory generator as part of their CoreGen. You plug in a bunch of variables for the size of the memory, width, depth, frequency, pipeline, burst, blah, blah and it spits out a supposedly working memory controller. They go so far as to say that every permutation has been verified to ensure correctness. The result is something like 7300 lines of verilog (or vhdl, your choice) across a bunch of directories and files. Keith

Sridhar Ayengar wrote: Works fine. The tools will warn you that you have an unused signal. It won't solve any complaints that tools may produce regarding not having a clock. However, I've never seen such a complaint from the Xilinx tools.

On 16 Nov 2011 at 18:44, Eric Smith wrote: FPGAs. Do you think you'd have any trouble working up an implementation of this 19-year old design in FPGA? http://brendaluderman.info/cv/papers/An_Asynchronous_Multiplier.pdf Nothing big, say 32x32 bit. I'm just trying to figure out how far this FPGA thing can be pushed. --Chuck

On 17 Nov 2011 at 0:03, Keith Monahan wrote: I think not quite what I had in mind. The self-timed design that essentially outputs a "done" signal when the product is finally formed. The verilog for this appears to reflect a fixed-time multiplier--at least there's no "done" output. Years ago, asynchronous computing was a hot topic--essentially, instructions were unclocked and took however long it required to signals to propogate through the logic to complete. That was the gist of Achronix' idea--that you could get some freakingly fast computation out of a clockless design. I also recall that the Philco System 2000 was one of the few commercial versions utilizing that idea. "Asynchronous" was part of their advertising campaign--and, for a very short time, they had one of the fastest transistorized machines. --Chuck P.S. I won't even broach the subject of reversible computation... :)

On 11/17/2011 01:01 AM, ben wrote: That seemed to have been the job of Windows Vista; fortunately it was short-lived so many of our machines survived! ;) -Dave -- Dave McGuire New Kensington, PA

On 17/11/11 1:47 AM, Chuck Guzis wrote: Everything is backwards. :( But it does expose their profit engine: Making you throw working things away as soon as possible. --Toby

I regularly use a SPARCstation 20. And I'm sure, especially here, that I'm far from the most extreme in that direction. So who's adapting? /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

On 17/11/11 9:05 AM, Mouse wrote: More to the point, why adapt? Older machines usually do the job. In this household, apart from the vintage machines, our daily use computers are 2007 Macbook (wife's), 2004 dual G5, 2005 PowerBook. Sometimes a 2004 PC (P4 HT 3.2) which is fast enough to run modern games, 720p video, etc. and was my daily Linux development machine when I worked from home. For a few weeks, the PowerBook was my main development machine at work recently; it was quite enough. No upgrades are planned or needed. My PowerPC Macs are really much faster than I need. --T

On 11/17/2011 12:43 AM, Chuck Guzis wrote: I've been doing a lot of research on some of Chuck Moore's new direct-execution Forth cores, like the F18A. They loudly claim to be asynchronous and clockless. Some very impressive designs are being churned out of his think tank. I have some samples on the way and am absolutely frothing at the mouth to slap some on a board. -Dave -- Dave McGuire New Kensington, PA

On 11/16/11 9:43 PM, Chuck Guzis wrote: I have been told that the 2000 was also unreliable because of this. I've never looked at the detailed design, though. Until the release of the CDC 6600, the follow-on Philco 212 was one of the fastest machines in the world. It would be interesting to find detailed hw docs on the 212. CHM has a CPU, but no detailed drawings of it.

From: Phil Budne Sent: Thursday, November 17, 2011 9:45 AM Hey, Phil! Long time. I don't think the crankiness in the PDP-6 was due to the async nature of the machine, but rather to the decision to go from the single connector on DEC's System Modules(TM) to connectors on two opposite edges of cards that were twice as large as System Modules.[1] Any component level failure required unsoldering the card from both sides of its placement in the machine, along with unsoldering one side of every board to which it was connected. Thanks for that pointer. I didn't know that was around. It certainly doesn't surprise me that Knight would have (had) it, though. [1] System Modules were DEC's first product, for those who don't know. Far larger than FlipChip(TM) cards, which were introduced with the PDP-7. Rich Alderson Vintage Computing Sr. Server Engineer Vulcan, Inc. 505 5th Avenue S, Suite 900 Seattle, WA 98104 mailto:RichA at vulcan.com mailto:RichA at LivingComputerMuseum.org http://www.LivingComputerMuseum.org/

On Nov 16, 2011, at 10:28 PM, Chuck Guzis wrote: You could do that. I've only skimmed the paper, so I can't say for sure if it does, but if it requires specific timing relationships between any of the asynchronous parts (e.g. X arrives later than Y), you might find it a little hard without setting lots of timing constraints on individual nets. The main reason for that is that while each LUT and flip-flop will have a basically identical propagation delay, the implementation tool will decide where they go on the die. Obviously, different routing lengths make a pretty big difference (even more so in silicon than on a board; sometimes on the order of several ns). I might give it a shot and see what comes out when I've got some spare time. - Dave

On Nov 16, 2011, at 1:15 PM, Chuck Guzis wrote: I'm not sure why you are saying this. You don't need a clock to implement combinatorial logic in a CPLD, or a FPGA. There's nothing stopping you from taking two inputs, anding them together and putting the output on another pin. The clock give the software a reference for timing analysis. But it's not required. -brad

On Nov 17, 2011, at 10:24 AM, Chuck Guzis wrote: Given the number of warnings the synthesizer probably threw up when it saw a large design without a clock it could infer ("NO CLOCK FOUND - WORLD PROBABLY ENDING"), I probably would have thought the same thing too. I think part of the problem is the industry's infatuation with fMax as a benchmark of tool quality; without a clock, there is no fMax, so the timing analyzer is a bit lost as to what to do. "So, uh, you got any setup time constraints for me? No? I guess... I guess I'll just find some propagation delays for you, then? Fine, but I'm not going to like it." Interestingly, though, you *can* do designs without a "clock" that use read/write strobes as they're intended to be used; the read/write strobes, for all intents and purposes, act as the clocks (typically, you'd use active-low #RD/#WR as the active clocks to the flipflops and use #CS as the clock enable). A lot of older chips worked that way (or at least similarly) internally anyway. The tool will give you some nonsense number for fMax (I mean, if you really wanted to do read or write strobes as a periodic clock, I guess you could), but it'll also give you setup/hold times and minimum pulse widths for high and low as well, which is much more useful in that scenario. - Dave

Eh? I _loathe_ simulation. I find nothing enjoyable about 'designing' on a computer at all. For almost everything I've ever designed or reparied I just use my brain. I have nop problems understnading hopw such things work. WHen I need a bit of assistance, I use a pocket calcualtor (seriously [1]). I've never needed anythhing more. [1] For example, I simluated the HP9830 memory control state machine using amy HP49G. I could haev done it by hand, I fully understnad what is going on, but working out the J's and K's 4 flip-flops by hand, and repeating it a dozen times is likely to involve at least one error, so I got my clacualtor to do it for me. The bit I enjoy is actually buidign the hardware. 'Getting my hands dirty' if you like. SOldering in the chips, wiring them up, etc. And as I said before, I'll do what I enjoy when it's for my hobby. That is one thing I dislike about FPGAs, certainly. On the other hand, I've had problems iwth (expensive commeraical) simualtrs that either fail to show glitches when they do exist, show glitches where the can't possibly exist, or generally have problems. It's amazing what you can still easily get. Alas (foer me) many of the more obscrue and intersting ones are no logner manufactured, but ther are plenty about. And it's aamzing what you can do with just gates and D-types, both of whcih are easy to get new. I guess you couldalways design the sort of board you need and eitehr etch it or get a PCB house to make it for you. And then wire-wrap on top of that. Quite honestly, ofr me, the less pre-built the better. Then I can use 'real' solder.... -tony

Precisely. As I said some messages ago, this is a hobby -- something you do because you enjoy it. IMHO the only requirewmnt for a hobby is that it doesn't have an adverse effect on others, it doesn't harm animals,, and things like that. Nobody else has to enjoy it. I cant;' see how wanting to design with papepr and pen and build by soldering up piles of components compeltely satisfies that. Or another example. There are people, I believe, who enjoy kicking and chansing a ball around an area of grass. Now, you'd not get me to do soemthing like that, not even at gunpoint, but I am not going to attempt to stop those that do enjoy it. That's their business, not mine. Quite apart from the fact that i's probably quicker to design it on paper... It needn't be that large. You cna fit at lest 30 DIL pacakges onto a eurocard (allowing space for handwiring). A cardcage full of such boards is easily enough for a CPU... Yes, that size will slow you down, but there are plenty of intersting things you can build if you want to Yes, had that too. YEs, I do want ot be warned if the CAD tool thinks my desin is a bad idea, but I also want to be able to say 'OK, build it just as I've shown it'. Alas my expereicen of FPGA tools is that they're very good at moaning about some tirival problems while not spottign major ones (hint : I've I've designed a lot of circuitry, and the output is always zero becuase I've accidentally tied an enable pin low rather than high i nthe schematic capture program, it's likely I've made a mistake!). Great -- NOT! And a lot of simulators have problems when you have significant external hardware connected to the IC. Somethat that can and does generate complex bitstreams linked to the circuit you're tryign to simulate causes a lot of headaches. At least one FPGA simulator I used didn't allow the imputs to the simulator to depend on the outputs from said circuitry -- in otehr words you coudl say that at time <t> these inputs must be high, those low, etc but you couldn;'t say that 'if these outputs are in states 01001 then 50ns later these inputs are 00001001' or whater. Simulating a device with external user program store was a right pain. Indeed there is. CAD tools do not turn a poor designer into a good designer. If the tools are genuinely good, they will make a good designer even better (and said 'good designer' will know when it's appropriate to use them). THis is not helped by many of the adverts for such tools... Alas yes... I agere with you here. I hate stipping an old board for parts if there;s any chance it copuld be used again i nthe original form. You new know when the machine it is to go in will turn up.. On the other hand, if some mroon has sawn off the gold-plated edge fingers (not realising that the board with the conenctors intact is worth a lot more to me than the cost of the gold in said plating) then I may well at least remove the more interesting parts... -tony

Who wrote that?!? Did not enjoy it? I rarely wanted to do anything else after having discovered FPGAs....! Can be fun - as long as it's just a handful of logic. With FPGAs you can do magic!

On 11/17/2011 10:25 PM, Chuck Guzis wrote: Me too; I've always been curious about them. I seem to recall them having been discussed here a year or two ago, with the conclusion that there wasn't enough documentation available to actually build anything around them. I would love for that to not be the case! -Dave -- Dave McGuire New Kensington, PA

Hmm. Of any use to anyone? The seller seems reluctant to name a price. Rare UNIVAC 1960's gold silver modular pcbs + HDD! http://www.trademe.co.nz/computers/vintage/auction-424967301.htm Auction's nothing to do with me, just noticed it tonight.