PDP-8/S Incompatibilities......

This is a followup to my previous email (attached)... I just finished reading the PDP-5 Users Manual - and discovered the following statement regarding the "operate instruction" (note: words in parentheses are mine): "Any logical combination of bits within this group (Group 1) can be combined into one microinstruction. For example, it is possible to assign ones to bite 5,6 and 11; but it is not logical to assign ones to bits 8 and 9 simultaneously since they specify conflicting operations (bits 8&9 are rotate right and rotate left). If RAL or RAR is specified, neither CMA or CML may be specified, and conversely. If RTL or RTR is specified, neither CMA, CML or IAC may be specified, and conversely." So the PDP-5 was even more restrictive with regard to microinstructions than the PDP-8/S! Matter of fact, I'm now even more impressed how Saul Dinman was able to design almost all of the functional capabilities of the PDP-8 into the PDP-8/S's compact package. In addition, while the PDP-8/S was only about half the performance of a PDP-5, the price of the PDP-5 was $27,000 while the price of the PDP-8/S was about $10,000 (4KW core, including TTY). In that context, it was a pretty good deal... Cheers, Lyle ------------------------------------------------------------------ Date: Wed, 16 Jul 2014 17:31:45 -0700 From: Lyle Bickley <lbickley at bickleywest.com> To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org> Subject: PDP-8/S Incompatibilities...... I've had my PDP-8/S up and running for some time - but have recently experienced failures using some PDP-8 software. My 8/S passes all the DEC diagnostics - and it runs FOCAL-69 and 71 perfectly. So I decided to track down what was causing some programs to fail - and I discovered that the problem is PDP-8/S incompatibilities. PDP-8/S "Reality" ----------------- The PDP-8/S User Manual lies! It makes the following claim regarding Group 1 Operate Instructions: "The only restriction on combining OPR 1 (Group 1) operations within one instruction, other than logical conflicts, is that a rotate operation (bits 8, 9 or 10) may not be combined with the increment AC operation (bit 11) since they are executed during the same bit times." I decided to test that claim on my PDP-8/S and got the following results (via single stepping through the test program below.) The "8/S" column is Link AC contents (L AAAA): *200 Page 1 1 0200 *200 2 /AC 8/S NOTES 3 00200 7200 CLA /0 0 0000 4 00201 7201 CLA IAC /1 0 0001 5 00202 7326 CLA CLL CML RTL /2 0 0002 6 00203 7325 CLA CLL CML IAC RAL /3 1 0003 8/I AND UP 7 00204 7307 CLA CLL IAC RTL /4 1 0001 8/I AND UP 8 00205 7327 CLA CLL CML IAC RTL /6 1 0003 8/I AND UP 9 00206 7215 CLA IAC RAL RAR /10 1 0003 6120 10 00207 7203 CLA IAC BSW /100 1 0001 8/E AND UP 11 00210 7332 CLA CLL CML RTR /2000 0 2000 12 00211 7354 CLA CLL CMA RAR RAL /3776 1 7777 8/I OR 8/L 13 00212 7350 CLA CLL CMA RAR /3777 1 7777 14 00213 7330 CLA CLL CML RAR /4000 0 4000 15 00214 7352 CLA CLL CMA RTR /5777 1 7777 16 00215 7333 CLA CLL CML IAC RTR /6000 1 0003 8/I AND UP 17 00216 7346 CLA CLL CMA RTL /7775 1 7777 18 00217 7344 CLA CLL CMA RAL /7776 1 7777 19 00220 7240 CLA CMA /7777 ? 7777 20 00221 7402 HLT 21 $ No detected errors No links generated Note that all of the CMA shift instructions failed - even though the test (from Programming Languages) thought they should work in pre-8/I machines. At first I thought my PDP-8/S was failing - until I found the following from the PDP-8/S FAQ (What is a PDP-8/S?): "Compatibility: The core of the PDP-8 instruction set is present, but there are a sufficient number of incompatibilities that, as with the PDP-5, many otherwise portable "Family of 8" programs will not run on the PDP-8/S. Perhaps the worst incompatibility is that the Group 1 OPR instruction CMA cannot be combined with any of the rotate instructions; as with the PDP-8, IAC also cannot be combined with rotate." I decided to understand WHY this happens - and the answer is in the PDP-8/S Maintenance Manual and the PDP-8/S schematics. I've abreviated the sequence of execution below. (The "Ax" references are bit timimg): Group 1 Instruction Sequencing ------------------------------ Fetch ----- A12 Set or Clear Link, Clear AC per instruction Execute ------- A00 For right rotation (A00-01), shift AC+L together once or twice per instruction A(00-11) IAC: Adds one to AC CMA: Complements the AC IAC*CMA: Complement and add one to AC Left Rotate: AC+L shifted right 11 or 12 times per instruction A12 IAC: Complements L on overflow (CMA appears in gating, but has no effect) As can be seen, while the system clears the AC and clears or sets the Link during Fetch - it rotates right BEFORE complementing the AC! It also attempts to execute a complement of the AC at the SAME TIME as a left rotate - which simply does not work! Finally, just to verify the correctness of the test program, I single stepped it on my PDP-8/E and got the same results as the SIMH trace below: SIMH PDP8 Trace of the above: ----------------------------- sim> sh cpu history PC L AC MQ ea IR 00200 1 7777 0000 CLA 00201 1 0000 0000 CLA IAC 00202 1 0001 0000 CLA CLL CML RTL 00203 0 0002 0000 CLA CLL CML IAC RAL 00204 0 0003 0000 CLA CLL IAC RTL 00205 0 0004 0000 CLA CLL CML IAC RTL 00206 0 0006 0000 CLA IAC RAL RAR 00207 0 0001 0000 CLA IAC BSW 00210 0 0100 0000 CLA CLL CML RTR 00211 0 2000 0000 CLA CLL CMA RAL RAR 00212 0 7354 0000 CLA CLL CMA RAR 00213 1 3777 0000 CLA CLL CML RAR 00214 0 4000 0000 CLA CLL CMA RTR 00215 1 5777 0000 CLA CLL CML IAC RTR 00216 0 6000 0000 CLA CLL CMA RTL 00217 1 7775 0000 CLA CLL CMA RAL 00220 1 7776 0000 STA 00221 1 7777 0000 HLT sim> Cheers, Lyle -- Bickley Consulting West Inc. http://bickleywest.com "Black holes are where God is dividing by zero" -- Bickley Consulting West Inc. http://bickleywest.com "Black holes are where God is dividing by zero"