On Feb 6, 2012, at 4:44 AM, Eric Smith wrote:
On 02/05/2012 10:31 PM, Mouse wrote:
But now I'm curious. What sort of performance
degradation does PNP exhibit? Slower switching? Higher power dissipation? And what's
the underlying difference behind it, do you know?
If I recall correctly (and
I'm no expert on solid-state physics, so I could easily be wrong), the difference
comes about because electron mobility in silicon is about three times the hole mobility.
Wikipedia says Si at 300K has electron mobility of 1400 cm^2/V*s, vs. hole mobility of 450
cm^2/V*s.
Nor am I an expert, but that's pretty much it. In CMOS ICs, the typical
practice is to double the channel width of the P channel to compensate for
the difference. This roughly equalizes the current of the two halves, but
the capacitance for the P transistor's gate is doubled because the gate
area is doubled. I don't recall how it affects bipolar devices, though I
imagine it's the same.
- Dave