31 Jul
2000
31 Jul
'00
1:55 p.m.
On 31 Jul 2000, Eric Smith wrote:
Additionally, VHDL doesn't represent the actually layout of the chip
at all. Many times the netlist generated by the synthesis tool has to
be hand edited to fix up the last few timing problems. This is similiar
to hand routing a few traces on a PCB that the autorouter can't handle.
I have been wondering how difficult it would be to pop the top off
an ASIC (perhaps one of the DEC gate arrays in my 11/750), photograph
it using the probe station at work, and reverse engineer the circuitry
based on the photographs. A program to recognize individual transistors
wouldn't be too difficult, then generating simple gates (nand,nor,invert),
To solve the
problem, they
created VHDL, a complex language used to describe the behavior of the
parts, from the very high level to the very low. It does not detail any
of the internal structure of the chips - just behavior.
Actually, VHDL can describe designs at any of several levels, including
a range from pure behavioral, as you suggest, to pure structural.
The most common uses of VHDL seem to be somewhere inbetween. Pure
behavioral descriptions are fine for simulation but don't tend to work
well for synthesis, so large designs are usually built as structural
descriptions of smaller behavioral subdesigns.
from them, the high level stuff like registers and
busses...
Anybody know of a tool to do something like that?
clint