- test-drb@ccmp.vtda.org - classiccmp.org

by allisonp＠world.std.com

<Allison wrote: <> I'd start with a 32bit PDP-8 (just add 20 more bits on the right side). <and in another posting: <> Me I'd do a stretch-8 for fun. though yours sounds interesting too. < <A Stretch-8 would require too much time spent on hacking -8 software for m <taste. Why not just build the equivalent of one of the DEC 18-bit family <members (PDP-4, -7, -9, or -15), since the PDP-5 and -8 are basically a 12- <version of the PDP-4. Then your project is at least compatible with <something, and can run some existing software (operating system, macro <assembler, Fortran). Several reasons. Don't know the 18 bit machines at all. I would want a machine that would fit in nx4 or nx8 format parts. I'd want a really simple instruction set as that simplifies the hardware ruling out the 10, 11 and vax. So streatching an 8 is it. Now a stretch-8 would have software as the bits added would only impact the address field. Makeing the top 5 bits and the bottom 7 behave as the normal 8 would make code port fairly reasonable. I've always found the 8 limiting in only one way, address space. Basically the Nova is a similar idea stopping at 16 bits. Allison

26 years, 10 months

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WD1002-05 Doc

by edick＠idcomm.com

A couple of weeks have elapsed since someone on this list asked for documents on the WD1002-05 Winchester/Floppy controller board. I have scanned my "preliminary" document and can make it available via email. It's "cooking" into final form on another machine right now, but I'd expect that since there are 44 pages the picture (TIF file) will be something just under 1 MB/page. This is a really big file and I may reduce its volume by converting it to compressed PCX format. If you want this document, please let me know how you'd like to have it formatted. Dick

26 years, 10 months

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FPGAs and PDP-11's

by IVIE＠cc.usu.edu

><A Stretch-8 would require too much time spent on hacking -8 software for m ><taste. Why not just build the equivalent of one of the DEC 18-bit family ><members > > Several reasons. [SNIP] I would want a > machine that would fit in nx4 or nx8 format parts. Bear in mind that some really interesting parts useful for this sort of thing (high-speed synchronous SRAMs, for example) come in x9 flavors to support parity on x8 byte machines. Roger Ivie ivie(a)cc.usu.edu

26 years, 10 months

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Fw: WANTED: 88110 docs -- specifically MC88110UM/AD

by geoffrob＠stmarks.pp.catholic.edu.au

Hi all, If anyone can help this guy, please contact him direct, I just fwd the msg >from the ng he posted in.... ----- Original Message ----- From: Allen Briggs <briggs(a)ninthwonder.com> Newsgroups: misc.forsale.computers.workstation,comp.sys.m88k,misc.forsale.computers.othe r.misc Sent: Sunday, 29 August 1999 9:05 Subject: WANTED: 88110 docs -- specifically MC88110UM/AD > I'm starting work on free OS port for Data General 88k systems. I'd > like to locate the user's manual for the Motorola 88110 processor. A > kind person has loaned me one for a while, but I'd really like to have > my own copy to use/mark up/whatever. It's no longer in print and not > available from the Motorola Literature Center. I already have the 88100 > and 88200 docs. > > If you have this book or know someone who might have this book getting > dusty on some shelf somewhere, please contact me. I'm willing to pay > something for shipping and something for someone's trouble in digging it > up and mailing it. > > Thanks, > -allen >

26 years, 10 months

1
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tek4015

by jritorto＠nut.net

does anyone have a pointer to programming information for this beast? I want a nice Mandlebrot set on my tek to amuse my guests. :-) jake

26 years, 10 months

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PDP era and a question

by edick＠idcomm.com

Whether this is correct or not, the real problem lies in that the data is available in the clear by virtue of the fact the unmodified data travels into the FPGA in a predfined way, allowing a simple and direct copying process to be set up. No reverse engineering is needed, just a rote copy. Dick -----Original Message----- From: Tony Duell <ard(a)p850ug1.demon.co.uk> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Sunday, August 29, 1999 1:05 PM Subject: Re: PDP era and a question >> > Anyway, the real point is that certainly for Xilinx FPGAs, if you buy the >> > official tools you get a program to 'reverse engineer' a bitstream back >> > to the CLB map. Converting that to a schematic is still a non-trivial task...

26 years, 10 months

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PDP era and a question

by edick＠idcomm.com

please see my embedded comments below. Dick -----Original Message----- From: Tony Duell <ard(a)p850ug1.demon.co.uk> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Saturday, August 28, 1999 11:27 AM Subject: Re: PDP era and a question >> >Please note, I am not saying that the FPGA manufacturers should support >> >all the possible choices of machine and OS. Just that I wish that _one_ >> >of them would provide enough information for me to support them myself. >> > >> The reality of the matter is that these device vendors, of whom I would >> assume it could be said they're in a good position to make such a >> determination, have decided that it's worth their effort to invest the >> effort and money in creating support tools for the PC running Windows 9x and >> not the PDP-8S or whatever, running something else. This is not my >> preference either, since I like and trust DOS much more than the WINDOWS >> varieties, but then, they no longer put out tools for the MAC either, not >> that I'd use one even if they were free. >> >> > >You are missing the point. I am not asking that the FPGA companies >produce/support tools that run on <whatever>. I am simply asking that >they allow me to create said tools. > Unfortunately, your desire to do that is in the toiled right along with the manufacturers' competitors' wish to learn what changes were made in order to field the last batch of "enhancements." Their perception is that too much detail about the parts' configuration details is too much detail about the inner workings of their product. It's their intellectual property, so if they wish to be able to protect it in court when someone steals is by whatever means, they have to show they've applied due dilligence throughout their operation to protect that information. If they don't, they run the risk that a competitor's lawyer will say, in court, that this information was not valuable enough to protect in the one instance, so why are they upset that someone acquired it through other means. It's a valid point. That's why many vendors don't give "free" copies of software anymore. The courts have found that if your product is valuable enough to prosecute someone for "stealing" it, then it should be so valuable that it can't be given away. Now, I'm not sure I buy all that, but that's the direction things seem to run. > >Think of microcontrollers for the moment, particularly the Microchip PIC. >I use that chip a lot. Now, I can either use the (free) Microchip >assembler/simulator that runs on PCs, or I can take the databook off the >shelf and write my own assembler/simulator. The necessary information is >given to do that. > >There is another reason I want this information. I want to create >self-modifying circuits, reconfigurable CPUs, etc. And I can't do that if >I am forced to use the manufacturers tools for every change in configuration. > > Not all vendors will give you all the necessary information to do that. Most makers of microcontrollers will, though. >Most (all?) of the existing work on such systems was done using the >now-discontinued Xilinx XC6200 series. Those were fully documented (I >have the data sheets). > > >[...] > >> >There was a _supplied_ program that would take a configuration bitstream >> >and turn it back into a CLB + interconnect map - essentially a >> >disassembler. Of course turning that map into a schematic was a lot of >> >work, but the 'secret' part was there. >> > >> >But no way would they tell us what any of the bits in the configuration >> >file actually meant. >> > >> >I am told they might have supplied some documentation under an NDA, but >> >that's no use for open-source software, of course. >> > >> Well, it's not likely that you'll encounter much cooperation in your effort >> to convince the world to share its secrets. These days, when patents are of > >Hmm... Since the architecture of the FPGA is already pretty well >described in the databook, releasing exactly how the bitstream configures >the chips is not giving that much more away. > >[...] > >> I'm surprised that there was a commonly available scf2xnf (or whatever it >> was called) translator, since that essentially reverse engineered your >> product for your competitor, but it would surprise me even more for the >> vendor to provide you the ability to see how they've enhanced their parts if >> that's reflected in their configuration files. > >The Xilinx tools I used (admittedly a few years old now) had a program >that let you edit the CLB/interconnect map yourself. And a program to >turn a bitmap into whatever file (xnf?) that this program would work with. > >Of course reverse-engineering a schematic from the CLB map is at least as >hard as reverse-engineering a large board of TTL chips. So it's not that >much help in copying a competitor's design. > Back in the early '80's I found that dirt simple. I can remember many a trade-show where my partner would, after we had examined a new product, buy me a cup of coffee and hand me a couple of extra napkins so I could draw a schematic of what I perceived the "new" product to be. Knowing how things worked and what the various TTL parts did made that into child's play. As a result, our products were almost always "better" than theirs. > >Any changes in the internals of the part (as it appears to the user - say >extra interconnect resources) were clearly visible using these tools and >were (IIRC) documented in the data sheets. As I said above, the data >sheets I have are reasonably details on what the chip contains and how it >works, but don't give the information to actually use it. > > >> Nevertheless, perhaps you need to back away from your devotion to the >> absolute notion of fully open source in favor of a really efficient, >> particularly cost-efficient, PDP whatever you want to build. If you need to > >I don't particularly want to make a PDP-anything. And if I did, I >certainly wouldn't use an FPGA... > You'd only do that if you intended to make your version better, faster, and less costly, along with less trouble to repair. > >If I use FPGAs (myself, for one of my own designs), I would want to >exploit the fact that they are reconfigurable parts. In other words, to >change bits of the circuit as the machine is running. Not just use them >as a replacement for a lot of TTL. > >> have sources in order to fix what you consider to be an annoying bug in the >> software tools with which the FPGA is to be devised, I'd point out that > >Hmmm... I've spent far too many long nights as a result of bugs in FPGA >tools. I'd much rather be able to see what they're doing to my circuit. > Well, if you're getting paid on time and materials, then it's someone else's worry, isn't it, if they specify a device with buggy software support. If you have your way, you specify a product which doesn't have those problems. > >> noone else is able to fix it either. Sometimes it's necessary to live with >> those "bugs" which annoy you most. > >Ah... But I have this ingrained objection to 'living with bugs'. If I >have a product (hardware, software, whatever) that doesn't work as I want >it to (or doesn't work correctly), I modify it. Period. > Perhaps that has more than anything else to do with your inability to find work. If you're so prone to get caught up in "fixing" what others don't even perceive to be broken, that you can't work with those tools, perhaps it's your outlook that needs fixing. In any case, perhaps a look in your own closet is warranted. I know I wouldn't hire someone who was not at all concerned about protecting intellectual property I had bought and paid for and who felt that it was more important to make a board easy to clone that it was to make it lower in cost and more reliable. Don't you think your outlook has some questionable perspective issues? If you're an engineer, your job is to solve the problems which confront you today with the resources at your disposal today, and not to lament the fact that someone built the XYZ round instead of square so it would stack neatly, and not to dream up technology which isn't yet commercially viable. Today's software isn't bug free, nor is it "open" enough to suit you. That is what's on the table, though. Refusing to use current hardware/software because it's not "open" enough isn't going to put a roast on the dinner table next Sunday, either. Maybe your talents would be better spent figuring out a better way to do what "the boss" wants, rather than trying to figure out a better thing to do. It's pretty apparent you have a good understanding of how the things work. It's also apparent you're capable of making the necessary leap. If you figure out a better way to do something on one of those computers you don't want with that OS you dislike, and sell it to .001% of all the users out there, you'll be wealthy beyond your wildest dreams. (You'll also develop different priorities where intellectual property is concerned!) OTOH, if you make an improvement to all the PDP-anythings still in use out there and sell it for 10x what it's worth, you'll still be as poor as ever. (well . . . maybe not poor . . . but the tax collector still won't remember you by name.) I haven't seen an FPGA (yet) which has "soft" configuration which can be changed on the fly. I think Triscend (www.triscend.com) may be heading in that direction, together with their 805x core. I've read a little about it, but as far as I know, the way to change it is to reset and reload the part, perhaps from a different configuration file. One thing I find shameful about the FPGA makers is that they have all this secrecy about one aspect or another of THEIR intellectual property as pertains to their parts, yet they do absolutely nothing to protect YOUR IP as it sits in a completely visible medium. If they would at least provide a feature to allow you to flash in a persistent encryption circuit not detectable from the outside but permanently associated with a given design . . . >-tony >

26 years, 10 months

5
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PDP era and a question

by allisonp＠world.std.com

<PDP-11 is certainly doable in the 4010 part, but I don't know if I could d <it and the 11/70 MMU or if I'd end up using two parts. These parts are Definately two or more to do 11/70 or the J11 (similar) as the MMU is a lot of registers (memory cells) and the CPU is not short on them either. <"slow" (50Mhz) which is a hell of a lot faster than a lot of -11's :-) In reality when you get the end of the design you find the interconnect delays internal to the chips will have you far slower. The J11 run with something like a 16 mhz clock for the early parts and the crop in the 11/93 I'd guess are closer or faster than 30mhz. <> What architecture? Microcoded or gates? Microcode requires an <> assembler, but might be quicker in the long run. < <Intel sued several people over the alleged use of Pentium microcode, <legally gates would probably be safer, also microcode == memory and memory <eats gates rapidly (even though the Xilinx have some cool features to avoi <that) and intel lost to nec as V20 microcode was actually wider! Microcode would be in external EEproms or some such to get the wide words needed to make the cpu fast. <Sounds like the definition of a hobby to me. :-) I'm going to do a PDP-8 o <my evaluation board, and after that will look at helping out on a PDP-11. Better place to start. The PDP-8 is not register intensive nor does it have many states that make sequential logic complex. The -8 has three 12 bit register and may be a temp (PC, MQ, ACC and MA(a temp)). The base PDP-11 (11/20, LSI11, T11) has 8 16bit registers plus flags and maybe temps for internal use. See why PDP-11 is more complex for FPGA? The base 11 has nearly 18bytes of ram never minding other flipflops needed! Hope this makes it more sense of the scale of complexity. The PDP-11 is the most CISC of the 16bitters and is only exceeded by the VAX. Allison

26 years, 10 months

5
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Dell "Oldest PC" winner on zdnet

by jeff.kaneko＠juno.com

On Sat, 21 Aug 1999 17:10:37 -0400 (EDT) Allison J Parent <allisonp(a)world.std.com> writes: ><> Is this the same Computer museum that parted out some PDP monsters ><> for saleable souveniers? ><> ><> Allison ><> >< ><I have a hazy recollection of that event, but I don't think(?) it is >the ><same one. This one exists in conjunction with Coleman College - >computer ><training. >< > >I'm happy to hear that. TCM does not rank high on my list of, things to >do to historical items. Preserving history, understanding it is very >difficult and an active wholsale destruction of any machine for money >is the same as tomb raiding for gold. ^^^^^^^^^^^^^^^^^^^^^ That's pretty much what my local scrapper does . . . . Jeff ___________________________________________________________________ Get the Internet just the way you want it. Free software, free e-mail, and free Internet access for a month! Try Juno Web: http://dl.www.juno.com/dynoget/tagj.

26 years, 10 months

8
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FS cheeep-Lotus Aproach 2.0 for Windows, new in box

by rhblake＠bigfoot.com

Still have a sealed copy of Lotus Appraoch 2.0 Database for Windows....and no use for it. It says it has both 5.25" (1.2mb) and 3.5" (1.44mb) disks. It states 286 or higher, Win 3.0 or higher, hard disk, EGA or better video, mouse, 2 mb RAM minimum.. It says it's compatible with files from dBase III & IV, Paradox, FoxPro, Oracle SQL 6.0 and SQL Server databases in native format.. It also states that's it's network compatible with Noverll Netware and Netware Lite, MS Lan Manager, Banyan VINES and LANtastic networks. Allows grpaihics imports in BMP, TIFF, PCX, WMF and EPS. $5.00 plus whatever the postage would be and it's yours. Drop me a direct note if interested.

26 years, 10 months

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Free DMF32 Dist Panel

by CLASSICCMP＠trailing-edge.com

Cleaning up the piles of stuff here, and decided to find something a good home rather than tossing it into another pile: Free to the first to offer to pay shipping ($3.20 USPS priority mail inside the US): A genuine DMF32 distribution panel, DEC part number 70-18754. Perfect for anyone with a DMF32 but without the cab kit! No cables included. -- Tim Shoppa Email: shoppa(a)trailing-edge.com Trailing Edge Technology WWW: http://www.trailing-edge.com/ 7328 Bradley Blvd Voice: 301-767-5917 Bethesda, MD, USA 20817 Fax: 301-767-5927

26 years, 10 months

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FPGAs and PDP-11's

by edick＠idcomm.com

I'm not nearly so concerned about the implementation details. Frankly, the FPGA vendors are all heading off in the wrong direction for implementation of those "old" processors and their peripherals. They give you 10 times I/O's you need and only half the routing resources. I'd much rather look at a plcc44 housing a 2500 CLB FPGA rather than a 500-pin FPGA housing what they claim is a 400K-gate equivalent. What's more, I'd rather see a 2 million gate "sea" of gates than a few dozen CLB's or macrocells, providet there were yards and yards of interconnection resources. That's not where they're headed. They want you to buy 32 ram bits with which to build a single nand gate. The PLD vendors aren't any better . . . their devices have always had too many inputs and not nearly enough buried resources for my taste. If I have to "do something" to a couple of inputs based on what a couple more do, then they work OK, but if I have to do a bunch of well-defined things based on what one input does, and generate one output based on a complex sequence of processes, always the same, however, then I have no choice other than the Scenix SX, which is a microcontroller. PALs and PLDs have never had the right input/output pin ratio, nor have they often had sufficient internally buried registers. Crying about it won't fix it, though. Dick -----Original Message----- From: Hans B Pufal <hansp(a)digiweb.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Saturday, August 28, 1999 12:13 PM Subject: Re: FPGAs and PDP-11's >Richard Erlacher wrote: > >> I've taken a good hard look at implementing the 6500 core in XILINX and find >> that performance, which is VERY much of interest, is impacted most by ALU >> design. > >No-one has mentioned the free IP project at <http://www.free-ip.com/> >which has a VHLD implementation of a 6502 now available. No idea of >performance on this, I have just begun to dabble in this area. > >I too bemoan the fact the full configuration specs are not availble for >the FPGA's. >A few years ago I was working for a company that had a Xilinx part >monitoring a processor bus. We wanted to dynamically reconfigure the >FPGA so that we could change the bus pattern it triggered on - no joy >though geting the necessary info. > >I see implementing old processors in FPGA's as a way of preserving those >the design of those processors. Yes, we would all prefer to have an >original, but practically speaking that is not possible. > >For some uses, a modern re-implementation or an emulator is better than >nothing at all. > >Regards > >_---_--__-_-_----__-_----_-__-__-_-___--_-__--___-__----__--_--__-___- >Hans B Pufal Comprehensive Computer Catalogue ><mailto:hansp@digiweb.com> <http://digiweb.com/~hansp/ccc>

26 years, 10 months

2
1
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PDP era and a question

by edick＠idcomm.com

please see embedded comments below. Dick -----Original Message----- From: Clint Wolff (VAX collector) <vaxman(a)oldy.crwolff.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Saturday, August 28, 1999 3:00 PM Subject: Re: PDP era and a question > > > >On Sat, 28 Aug 1999, Richard Erlacher wrote: > >> please see my embedded comments below. >> >> Dick >> <snip> >I saw a blurb about that several years ago in one of the trade rags. >Basically, the part was sector based (not their name for it). You could >reload a portion of the FPGA while the rest continued to operate. The >example that was given was loading different image processing algorithms >into the chip while the rest of the chip continued to pull in and output >the video stream. > I've see writing, but not authoritative writing about this. I don't consider marketing departments capable of authoritative writing, by the way. > >> One thing I find shameful about the FPGA makers is that they have all this >> secrecy about one aspect or another of THEIR intellectual property as >> pertains to their parts, yet they do absolutely nothing to protect YOUR IP >> as it sits in a completely visible medium. If they would at least provide a >> feature to allow you to flash in a persistent encryption circuit not >> detectable from the outside but permanently associated with a given design . >> . . > >Publishing what each bit in the bitstream did would get your competitor >half way to having a schematic of your design. > >clint > That's not as much a problem as allowing him to dupe your board (Plenty of PC market boards have just the one major ASIC and a large and price-sensitive market which a $1 lower price with take over.) and the contents of your configuration EEPROM, then buy the same part from XILINX or whoever supplies your parts, build them down the very street in TAIPEI from where yours are made, then sell your work to the public, documentation and all, leaving you with a market saturated with counterfeits of your product and a HUGE support burden to pay for with your non-profits. > Dick

26 years, 10 months

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HELP for ML command

by hiyama＠abit.co.jp

Hi Dear Please advice for Mailing list usage to change the mail address. Thank you very much. Takeo

26 years, 10 months

3
3
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FPGAs and PDP-11's

by edick＠idcomm.com

Well, the 650x is a VERY thrifty architecture. It has no memory-to memory operations, nor does it have any operations involving more than one register at a time. Additionally, if one chooses to implement it in the way the original manufacturers did, the ALU serves, not only to operate the instruction set, but also is used to operate on the PC and SP as well. This save LOTS of resources in the construction of the associated counter chains. That's not to say it's easy to implement this architecture in an efficient way, though. You have to look at another aspect of FPGA's however, and that's the combined effect of routing and resource utilization. The ALTERA folks may claim to have implemented this architecture in only 7% of the resources of the part, but at what cost? In general, a substantial portion of the resources available in a device, in terms, for example, of raw gate count, is lost in the implmentation of a design. In each logic cell or logic block, there are resources which the marketing department proudly counts and advertises, yet which, once a part of the logic cell is used, are gone forever and unusable. The routing is another factor which plays a big role in the way FPGA's work out. Allocating a given routing resource in a certain way can effectively render other logic resources unusable because of lack of interconnection resources with which to do that. Consequently, routing in a manner essential to a given level of performance for some of the device resources can render other resources unreachable for any practical purpose. The marketing guys don't consider this when publishing their full-color glossy brocheures, though. If they go to work, they'll say, well, this nand gate is only 6% of a CLB, even though the entire CLB is used up, say, and that pipeline register used to synchronize these functions is only 12% . . . when in reality as much as 50% of the array may be consumed by such a design, and the remaining "half" may be very difficult to utilize beyond 15%. I've taken a good hard look at implementing the 6500 core in XILINX and find that performance, which is VERY much of interest, is impacted most by ALU design. Now, the Virtex CLB allows a single CLB to function as a two-bit full-adder. If one wants the best performance/resource allocation tradeoff, I'm nearly convinced that the best way might be to design it with a 2-bit ALU slice because the resource consumption is small yet the delay for a 2-bit registered implementation of an 8-bit ALU would be just as fast as an 8-bit implementation because of the carry delay from stage to stage. It appears to me that the rate-determining step, then, becomes how fast a clock can be routed through the array. In the case of the 2-bit slice, it doesn't have to propagate very far to get the job done. With an 8-bit implementation, there's a lot more routing delay, and at least four times as much delay per cycle in order to allow the carry to settle. Since the ALU is used more than once per machine cycle . . . (see where all this leads?) Dick -----Original Message----- From: Alex Knight <aknight(a)mindspring.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Friday, August 27, 1999 9:58 AM Subject: Re: FPGAs and PDP-11's >Hi, > >Another data point w.r.t. implementing microprocessors in FPGAs >involves the 6502: When Altera was initially rolling out their 10K >family of FPGAs, one of their marketing charts shows how they >built a 6502 processor inside a 10K50 device using only 7% of >the FPGA resources. > >Regards, >Alex Knight >Calculator History & Technology Web Page >http://aknight.home.mindspring.com/calc.htm > >At 06:05 PM 8/26/99 -0700, Chuck wrote: > >>I did a preliminary "floor plan" for the PDP-8 and it used just under 1/3 >>of the 4010 (or 75% of a 4005 given the routing issues, which leaves enough >>to do an M8660 serial port.) >> >>--Chuck >> >>

26 years, 10 months

4
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FS: Old UNIX serverware for 386 cpu

by ds284＠hotmail.com

FOR SALE: Approx. 18 pounds of software/manuals, consisting of two packages; all sells for one money. Best offer over $24 takes. Deadline for offers is September 11, 1999. * Retix Open Server 400 for UNIX MH-4410 ISC/SCO, Ver. 1.41 * Retix SMTP Gateway to X.400, Ver. 2.01 BOTH are provided on dual-format hi-density floppies. Software disk packages have been opened, but appear to show little usage. Sys. Requirements: ------------------ * SCO UNIX Sys. V/386, Rel. 3.2, Ver. 2.0 and 4.0 * Interactive UNIX Sys. V/386, Rel. 3.2, Ver. 2.2 and 3.0 and 386 cpu, 4 or 8 Mb RAM, 100 Mb disk space, including OS; hi-density floppy Ships from Laurel, Maryland 20707 USA only, please. ============================================================= ______________________________________________________ Get Your Private, Free Email at http://www.hotmail.com

26 years, 10 months

1
0
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FPGAs and PDP-11's

by edick＠idcomm.com

please see comments embedded below. Dick -----Original Message----- From: Pete Turnbull <pete(a)dunnington.u-net.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Friday, August 27, 1999 4:41 PM Subject: Re: FPGAs and PDP-11's >On Aug 27, 20:46, Hans Franke wrote: >> Subject: Re: FPGAs and PDP-11's >> > Well, the 650x is a VERY thrifty architecture. It has no memory-to >memory >> > operations, nor does it have any operations involving more than one >register >> > at a time. >> >> TXA ? (Don't kill me :) > >And the indexed instructions such as ADC (nn,X), of course, and TSX, etc. > This is a case like the TXA, etc, which is a simple transfer from one register to another with no ALU operation. > >> > much delay per cycle in order to allow the carry to settle. Since the >ALU >> > is used more than once per machine cycle . . . (see where all this >leads?) >> >> More than once ? >> Maybe I'm just blind, but I cant see more than one ALU op per cycle. > Well, on each cycle it flows the PCL through the ALU, adding zero with carry. The indexing operations and stack pointer op's also do arithmetic on the ABL and SP. Likewise, the INC and DEC instructions flow data from the register block to the register block through the ALU. Still, there are no register operations which require access to more than one register's contents at a time. The critical issue being that the registers can simply be implemented in a RAM. In fact, it appears that the RAM block might best be implemented in an inverting RAM like the 74189 (actually a 16x4, but two would work) because the arithmetic unit might work quite well as a simple adder/subtractor, with a multiplexer as the shifter unit. The fact that this RAM has separate inputs and outputs makes the TTL model very simple. > >Some of the indexed instructions do. Once to add the offset, and once for >the operation requested, eg ADC (nn),Y. > The indexing operations involve arithmetic on memory address operands rather than on register contents. The instruction contains the absolute address or a pointer to it, and an index register contains an offset. Arithmetic is done on the address components and only on one element in the register set. Either one or two address bytes are part of the instruction, depending on the mode, and the index register contains the offset to be added to the low address byte either from the instruction or from the table to which a zero page pointer directs it and 16-bit arithmetic is done on that using only one byte from the register set. These indexed instructions using indirection take as many as 6 (7 if a page boundary is crossed) cycles. The arithmetic can always be done using the ALU, however. >-- > >Pete Peter Turnbull > Dept. of Computer Science > University of York

26 years, 10 months

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mailing list down????

by macierno＠cvm.msstate.edu

Is the mailing listt down, havn't seen any activity for the past day or so! mark acierno ------- ICQ 40439199 http://www2.msstate.edu/~mja2

26 years, 10 months

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FPGAs and PDP-11's

by pete＠dunnington.u-net.com

On Aug 27, 20:46, Hans Franke wrote: > Subject: Re: FPGAs and PDP-11's > > Well, the 650x is a VERY thrifty architecture. It has no memory-to memory > > operations, nor does it have any operations involving more than one register > > at a time. > > TXA ? (Don't kill me :) And the indexed instructions such as ADC (nn,X), of course, and TSX, etc. > > much delay per cycle in order to allow the carry to settle. Since the ALU > > is used more than once per machine cycle . . . (see where all this leads?) > > More than once ? > Maybe I'm just blind, but I cant see more than one ALU op per cycle. Some of the indexed instructions do. Once to add the offset, and once for the operation requested, eg ADC (nn),Y. -- Pete Peter Turnbull Dept. of Computer Science University of York

26 years, 10 months

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FPGAs and PDP-11's

by edick＠idcomm.com

You're quite right, but I actually meant that there aren't any instructions which operate on more than one register at a time using the ALU with more than one register for inputs. If you consider the instructions which do use the ALU, you can see that a single register set, implemented as a RAM block would allow you to transfer from the register RAM outputs through the ALU and back into the registers in a single operation. That's what makes this architecture so thrifty, as it means that you can send the PCL through the ALU, adding a zero with carry set, and back to PCL, setting a carry flag if that's applicable and if carry's true, then adding zero with carry to PCH again storing the result in the source register. In reality there are several operations which use the register set as both source and destination, but none which use TWO registers as operands and then use the registers as a destination as well. What that allows is that you use a ram location as PCH, one as PCL, one as SP, and one as each of the registers, X, Y, and A. Because of the way the thing works, the logic paths are simple and straightforward to steer via a single data bus from the ALU back to the register inputs. That explains why there's an extra cycle needed whenever addressing across a page-boundary occurred. If you constrain your thinking to the logic components which were available back in the mid '70's, e.g. 74181, 74189 (for the register set), and consider what was on the data bus when a "float" was encountered during a read, namely the PCH, you begin to see the rudiments of this processor's internal architecture. Moreover, if you think of the "pipleining" used by the 650x in terms, not of synchronous pipleining as commonly used today, but of pipelining the control structure so that the data flow could be managed not with edge-triggered flip-flops but with gated latches, ala-7475, then you see how the timing was developed. The ALU was always a path for data from the registers to the registers' input bus. The data bus output latch was, of course taking inputs from this as well, and the output data, coincidentally followed the rising edge of the phase-2 clock by about the same amount of time as the valid addresses followed the falling edge. Since register-to-register operations had to flow through the ALU, and since the registers had a common input path, only one register could be targeted at a time. Since the register set is a RAM, you couldn't do it any other way. If separate registers had been used, the number of multiplexers would have been made the chip much larger. The operations on the accumulator which required either immediate data or data from memory were served by an impending operand register which was loaded from the last memory fetch prior to the execution of the operation. This action took a cycle, but didn't involve the data bus, so that what when the processor fetched the next opcode, knowing that the impending operand register was not involved in that operation and knowing that the one register which would be unaffected by an opcode fetch was the IOR. Dick -----Original Message----- From: Hans Franke <Hans.Franke(a)mch20.sbs.de> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Friday, August 27, 1999 12:45 PM Subject: Re: FPGAs and PDP-11's >> Well, the 650x is a VERY thrifty architecture. It has no memory-to memory >> operations, nor does it have any operations involving more than one register >> at a time. > >TXA ? (Don't kill me :) > >[...using 'only' one ALU...] > >Not uncommon back than and very efficient. I still belive the 65xx >is one of the best - the instruction set is well defined to get >the maximum out of a minimal hardware. You can see the function >blocks klick just by looking at the instructions. > >> [... about resources] > >Exact, thats the main Problem with most %used numbers. > > >> I've taken a good hard look at implementing the 6500 core in XILINX and find >> that performance, which is VERY much of interest, is impacted most by ALU >> design. Now, the Virtex CLB allows a single CLB to function as a two-bit >> full-adder. If one wants the best performance/resource allocation tradeoff, >> I'm nearly convinced that the best way might be to design it with a 2-bit >> ALU slice because the resource consumption is small yet the delay for a >> 2-bit registered implementation of an 8-bit ALU would be just as fast as an >> 8-bit implementation because of the carry delay from stage to stage. It >> appears to me that the rate-determining step, then, becomes how fast a clock >> can be routed through the array. In the case of the 2-bit slice, it doesn't >> have to propagate very far to get the job done. > >Well, after all, any serious attempt to bring a 6502 into a FPGA >will be about speed - and saving resources might not be the >primary goal. > >> With an 8-bit >> implementation, there's a lot more routing delay, and at least four times as >> much delay per cycle in order to allow the carry to settle. Since the ALU >> is used more than once per machine cycle . . . (see where all this leads?) > >More than once ? >Maybe I'm just blind, but I cant see more than one ALU op per cycle. > >Gruss >H. > >-- >Stimm gegen SPAM: http://www.politik-digital.de/spam/de/ >Vote against SPAM: http://www.politik-digital.de/spam/en/ >Votez contre le SPAM: http://www.politik-digital.de/spam/fr/ >Ich denke, also bin ich, also gut >HRK

26 years, 10 months

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IBM 5100 Serial Number Project Redux

by wsmith＠gj.com

My serial number project is going slowly. I only received two responses (thanks, Charlie and Joe) and so my sample set has a woeful three date points:13352 (Charlie's), 13513 (mine, sold 1/77) and 14213 (Joe's, sold 9/77). Perhaps a rate of about 1000 units per year in 1977, but too little info to tell. If this rate is correct, I would suspect the the numbering began around 12000 or so. C'mon everybody, have a look at the back of your 5100 (the number is engraved into the back of the case, usually preceeded by a "10-") and keep those numbers coming. Thanks.

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PDP era and a question

by edick＠idcomm.com

addressing only the comment quoted below . . . Really, Tony, I think you overemphasize the importance of the individual user to the semiconductor manufacturers. The level of competition for the FPGA business has escalated to where the development software, previously costing several K-bucks US, now costs as little as $100, and, in the case of ALTERA, is quite free. Now, that's not the complete package with all the bells and whistles, but it's enough to build a device from start to finish. I really doubt that it would turn out to be illegal to take the old 11-70 or whatever schematic and essentially clone it in an FPGA, but I doubt a clever rebuilder would want to do that anyway. It might be either equally good in the end product to build the thing so it's thriftier than the TTL design would be, yet still a bit faster, or so it's quite a bit faster and perhaps not quite the same. It doesn't have to be identical to run the same code. The technology in FPGA's these days is such that it enables devices to operate between 10 and 50 times the speed of the old TTL logic designed in the '70's. That doesn't mean you can take a '70's design and "transliterate" it and make it run lots faster, though that is conceivable. What it does mean is, similarly to translating poetry from one language to another, logical constructs can be ported from one technology to the other, changing the outward and physical details of the circuitry, yet preserving the upper-level sense of the logic in such a way that it capitalizes on the available enhancements, thereby yielding a product which is quite different >from the original, yet performs the identical task in more or less the same way at MUCH greater speed, or MUCH lower complexity, and, hopefully lower cost. Once you've translated a poem, you've done the same work as the poet, more, in fact, yet you've created nothing new. OTOH, in the case of the computer, redesigned to capitalize on new technology, I believe you could argue that it is, indeed, something quite new. If it were to be generated for, say , a XILINX part of the 5200 series, it would not necessarily be very costly, nor would it be difficult once one has the original print set as crib sheets. What's more, it would potentially be so much faster than the original, and take up so much less space, e.g. a 2" square package, you could build the MMU into it and interface it directly to the DRAMs, maybe adding a circuit to copy the ROM code into RAM during its boot. Schematic entry would be the easiest way to clone the prints, but HDL is considered by many to be the best way to implement an architecture, the behavior of which is well defined and understood. If you build your device in VHDL or VERILOG, it is inherently portable, since both XILINX and Altera, among others, support both. Building a device like this in several parts merely ups the cost, since resources are consumed by the interconnection between them. Time is used up in the interconnections as well, so performance would be lower. When all is said and done, the single FPGA is the "right" notion. I don't think the FPGA makers would care if you use their parts to craft a device. If you have the HDL code, nearly any distributor will provide you access to the resources to implement it in a product they sell, provided you buy the parts from them. They cost a few dollars in small quantity, but if you say the right "things" when approaching them, and seem sufficiently eccentric, they'll treat you right. Dick -----Original Message----- From: Tony Duell <ard(a)p850ug1.demon.co.uk> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Thursday, August 26, 1999 4:08 PM Subject: Re: PDP era and a question <snip> >I am sure it's illegal to (say) take the PDP11/70 printset, modify it so >that it could work in an FPGA (and there would be significant mods), and >implement it like that. I am not so sure there would be any problem if >you just took the instruction set and designed a CPU to run it without >using any DEC printsets. People have done this with the PDP8 for many years. > > >> >> Given the complexity of the 11/70 CPU it should be possible to put the >> entire thing inside a relatively inexpensive FPGA these days. Given >> something like NetBSD that is already multi-architecture aware, that would >> make it possible to have an open source OS running on it. We could >> potentially get to a system that was completely "open hardware." (ie anyone >> could build one with no royalty requirements, and hackers could build them >> for fun.) > >If you wanted to do this, then it would probably be easier to design a >CPU from scratch (which is not hard) that was better suited to running *BSD. > >Also, be warned that if you're going to use FPGAs you have to use the >manufacturer's tools which are not going to be Open-Source, and which are >not going to run under Open-Source OSes. Several of us have moaned about >this for quite a time, but alas there are no 100% documented FPGAs out >there, and if anyone manages to crack the configuration format, you can >bet the manufacturers will change it, along with a 'free update' to the >official tools. > >In other words, the machine won't really be free for anyone to construct. > >-tony >

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PDP era and a question

by allisonp＠world.std.com

< How many gates is a single chip processor going to use? And how < expensive is an FPGA that size. Or are large PALs a better choice < (free tools for AMD/Vantis MACH series, and Altera's entry level < parts) Figure well in to the 10000+ region. The PDP-11 looks simple but it's not! < What to use for a system. If I use a QBus based system (I have < several available) what are the timing requirements? Is there < a doc for this? Or Unibus? Or (my current favorite) Socket-7... Least significant consideration. First the chip/chips. < What architecture? Microcoded or gates? Microcode requires an < assembler, but might be quicker in the long run. Microcoded, all of the chip level 11s are (LSI-11, F11, T11, J11). < And when its all done, what is it really good for? How many < "hardware hackers" are interested in building CPU boards, and < are willing to share the cost of laying out and manufacturing < PCBs? Look a any PDP-11 ask that question, theres your answer. <I will probably make a stab at it, but depending on life, might not <ever finish... It's doable, the docs needed are commonly available. Costly. Allison

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Evovling computers (Was Re: PDP era and a question)

by max82＠surfree.com

><http://www.newscientist.com/nsplus/insight/ai/primordial.html> Wow, thanks for that link, John. I was not aware that this type of 'genetic programming' had actually come this far. The one thing that bothers me about it is that the scientist does not know how it works. Although I realize that it has to come to this at some point, I would really like to know how the machines which I create function. Besides for the fact that I would then be able to fix them, I could also rule out the possibility of this machine trying to take over the world or some such thing (possible with an advanced enough machine).

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PDP era and a question

by edick＠idcomm.com

The rule of thumb back in the '70's was that TTL was "good" to 25 MHz. Current generation FPGA's routinely operate at 10x that speed, while, in reality, it was an exceptional TTL design of the '70's that would allow a significant bit of circuitry, e.g. a FIFO or a synchronous state machine, to operate across more than a very few bits at that speed. Typical prop-delays of 10-15 ns would add up quickly. (remember that we've since then learned about pipleine registers, which were not in common usage then.) The latest (e.g. VIRTEX) families boast synchronous performances of 500 MHz for such structures, though their CLB's (configurable logic blocks) have prop-delays of under a ns and clock-to-q prop's in that range as well. Those CLB's are really lookup tables in which you program a random function of up to 5 variables, hence get the same prop whether it's a nand or an xnor. It would take a clever designer indeed to get anywhere near the top level of performance with a rework of the PDP-11 processor, but it's been attempted. There are more than one of them out there, though I haven't kept up on that. Nevertheless, if you do it, particularly in a popular HDL, you're developing essentially your own intellectual property, and in a portable medium which you can use with any vendor's product. Dick -----Original Message----- From: allisonp(a)world.std.com <allisonp(a)world.std.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Friday, August 27, 1999 6:35 AM Subject: Re: PDP era and a question >> The technology in FPGA's these days is such that it enables devices to >> operate between 10 and 50 times the speed of the old TTL logic designed in > >Old ttl was nowhere near that much slower. The lowly 7400 in 72 was >comfortablly under 15ns, true the FPA part may be under 1ns now but... >that's not 50X! Of course adding interconnection delays and other factors >the 10x number is very honest. > >> the '70's. That doesn't mean you can take a '70's design and >> "transliterate" it and make it run lots faster, though that is conceivable. > >This is true of any from one logic system to another. PDP-8 for example >used a lot of "wired or" and similar logic in the data paths to conserve >gates. Of course that was a slower way to do it but lower cost too. >So a design translation can buy speed at the cost of logic or design >effort. > >> Schematic entry would be the easiest way to clone the prints, but HDL is >> considered by many to be the best way to implement an architecture, the >> behavior of which is well defined and understood. If you build your device >> in VHDL or VERILOG, it is inherently portable, since both XILINX and Altera, >> among others, support both. > >VHDL is the way to go but developing the description would be the real >work. > >> access to the resources to implement it in a product they sell, provided you >> buy the parts from them. They cost a few dollars in small quantity, but if >> you say the right "things" when approaching them, and seem sufficiently >> eccentric, they'll treat you right. > >Roger that. Besides, they know if you do one your likely to use it for >other things (drag factor). > >Allison >

26 years, 10 months

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PDP era and a question

by jfoust＠threedee.com

Here's an interesting twist: genetic algorithms in FPGAs, discriminating words and tones: <http://www.newscientist.com/nsplus/insight/ai/primordial.html> - John

26 years, 10 months

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Harris Mainframe? (fwd)

by siconic＠jasmine.psyber.com

Can someone help this guy out? Please reply to the original sender. Reply-to: garald4(a)net-link.net ---------- Forwarded message ---------- Date: Thu, 26 Aug 1999 18:10:01 -0700 From: Garald Austin Barton IV <garald4(a)net-link.net> To: vcf(a)vintage.org Subject: Harris Mainframe? I am a college student looking for information about a mainframe. Harris (Data Communications Division) Model No. KH174-32R Made approx. 1984 Thank you for your time. Any response is appreciated. garald4 Sellam Alternate e-mail: dastar(a)verio.com ------------------------------------------------------------------------------- Puttin' the smack down on the man! Coming this October 2-3: Vintage Computer Festival 3.0! See http://www.vintage.org/vcf for details [Last web site update: 08/17/99] [Last web site update: 08/17/99]

26 years, 10 months

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PDP era and a question

by danburrows＠mindspring.com

>Other companies have made drop-in PDP-11 replacements over the years, too. >QEI (based in MA) makes drop-in upgrades for 11/34's, 11/44's, and >11/70's, and Setasi (in Florida) makes drop-in upgrades for 11/70's. Correction it is QED in MA. I have one of their J11 upgrades for 11/24's - with docs. QEI is a DEC dealer. There is also Nissho that I have seen info on but have never played with. >Yes, I have run RT-11, RSX-11, and 2.11 BSD on systems that didn't >have a single DEC hardware component in them. (For example, a Mentec >M100 CPU and Andromeda disk controller in a third-party Q-bus backplane.) > The M100 I have in hand still uses the J11 however. I think the latest ones they went away from real J11's. Dan

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PDP era and a question

by CLASSICCMP＠trailing-edge.com

>Making a processor is not hard (although FPGAs might make it harder than >just using simple TTL chips -- some of the manufacturer's claims on this >are plain false). I'd not try to re-implement the PDP11 unless you had a >good reason to do that -- rather, design an instruction set and >architecture and implement it. I agree 100% here. *Especially* if your goal is to run NetBSD or Linux or (insert popular Unix-like free OS here). These OS's simply don't fit well into the 16-bit virtual address space of an -11 (2.11 BSD has many of the features of modern Unices, but doesn't have the wastage found in NetBSD or Linux). A small, RISC-ish instruction set is perfect for implementing NetBSD on. Things get a bit more complicated as you add the necessary memory management, of course! -- Tim Shoppa Email: shoppa(a)trailing-edge.com Trailing Edge Technology WWW: http://www.trailing-edge.com/ 7328 Bradley Blvd Voice: 301-767-5917 Bethesda, MD, USA 20817 Fax: 301-767-5927

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PDP era and a question

by allisonp＠world.std.com

<are plain false). I'd not try to re-implement the PDP11 unless you had a <good reason to do that -- rather, design an instruction set and <architecture and implement it. Good point. If you want a good -11, find one. Myself I find the 11 to be more of a software playground with that instruction set. If I were doing my own, well then, it's a matter of what if... I'd start with a 32bit PDP-8 (just add 20 more bits on the right side). I'd keep the PDP-8 instructions (add a few more microcoded ones for byte ops), addressing and IO. With 32bit addressing and 27 bits direct addressing in both current page and page 0 it would make a good enough graphics cpu to be useful, if fast. Even if scaled back to 24 bits it would be interesting. Also very buildable using 74F parts. At the same time old PDP-8 code could be "lofted" to run on it so a OS would be possible in a reasonable time. With a little effort a .3us instruction cycle is very doable (3mips!) maybe even faster. Pentium no, but fast enough to make some sense. Allison

26 years, 10 months

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PDP era and a question

by cmcmanis＠freegate.com

As was pointed out on the NetBSD list, Compaq has officially End-of-lifed (EOLd) the VAX architecture. This follows a trend of having EOLs the -8, -10, -11, and now VAX series. I suggested to some folks, off list, that perhaps DEC should make the PDP-11 architecture "open source" in the sense of allowing anyone to produce PDP-11 capable processors but was told that Mentec has purchased the rights to the PDP-11 architecture from DEC. What's up with that? True? False? Kind-a true? (I know Mentec sells PDP-11 compatible computers) Given the complexity of the 11/70 CPU it should be possible to put the entire thing inside a relatively inexpensive FPGA these days. Given something like NetBSD that is already multi-architecture aware, that would make it possible to have an open source OS running on it. We could potentially get to a system that was completely "open hardware." (ie anyone could build one with no royalty requirements, and hackers could build them for fun.) --Chuck

26 years, 10 months

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PDP era and a question

by allisonp＠world.std.com

<Can you restrict an architecture like this? I've never heard of an <Interlectual Property case being based on the fact that the 2 products <(CPUs) run the same instruction set. DEC and oh I forget on PDP-8, NEC and intel on 8086/V20 and plenty more. <Also, be warned that if you're going to use FPGAs you have to use the <manufacturer's tools which are not going to be Open-Source, and which are <not going to run under Open-Source OSes. Several of us have moaned about Not all are restricted to one vendor. Just why bother. Now, if you really want to build a PDP-11 of any kind yank the t11 chip >from a dead Vt240/241/RQDXn and build one to suit ones self. It's a real PDP-11 and it does run RT11 (assuming standard devices) as the falcon card does. If 64kb of addressing is not enough try building a mapper like most of the 11s have, a couple of 74189s should do. This is a nice 40 pin dip and not much hard to design with than z80 though the z80 never offered things like selectable 8/16bit bus or selectable start/restart addresses not to mention cycle and clock options. Performance is better than LSI-11 if memory runs without wait states. Creating the chip is half the task, putting it to work is the real fun. Allison

26 years, 10 months

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PDP era and a question

by CLASSICCMP＠trailing-edge.com

>I suggested to some folks, off list, that perhaps DEC should make the >PDP-11 architecture "open source" in the sense of allowing anyone to >produce PDP-11 capable processors but was told that Mentec has purchased >the rights to the PDP-11 architecture from DEC. What's up with that? True? >False? Kind-a true? (I know Mentec sells PDP-11 compatible computers) Mentec sells several different kinds of PDP-11 compatible computers, some of them based on the DEC/Harris J-11 chipset, others based around custom FPGA's. See http://www.mentec.com/ for a rundown. Other companies have made drop-in PDP-11 replacements over the years, too. QEI (based in MA) makes drop-in upgrades for 11/34's, 11/44's, and 11/70's, and Setasi (in Florida) makes drop-in upgrades for 11/70's. I don't think there's any legal impediment to picking up a PDP-11 processor handbook and implementing your own hardware design of the architecture. (Just as there's nothing stopping you from building a PC-clone motherboard or a x86 CPU based on published specs.) In the end, you'll have to be sure that you aren't stepping on anybody's patents, of course. >Given the complexity of the 11/70 CPU it should be possible to put the >entire thing inside a relatively inexpensive FPGA these days. The faster Mentec boards are heavily built around FPGA's, they are certainly one common way to go for such things. > Given >something like NetBSD that is already multi-architecture aware, that would >make it possible to have an open source OS running on it. I'm not sure that NetBSD is necessarily the way to go. It hogs memory like crazy (not something you want to do in the 16-bit virtual address space of an -11), the standard compiler (gcc) is a real CPU-eater compared to "native" compilers, and changes to the predominantly Intel-based sources take a long time to get "fixed up" for the less common architectures. Heck, the current Vax port is actually less functional (in terms of stability and hardware support) than it was three years ago. OTOH, for $100 you can get a Unix source license ( see http://minnie.cs.adfa.oz.au/PUPS/index.html ) and run 2.11BSD on your hardware, which gives you just about everything you could want from a modern Unix (including networking) that will actually fit. And it doesn't use gcc - that's a *real* advantage on an -11! Yes, I have run RT-11, RSX-11, and 2.11 BSD on systems that didn't have a single DEC hardware component in them. (For example, a Mentec M100 CPU and Andromeda disk controller in a third-party Q-bus backplane.) -- Tim Shoppa Email: shoppa(a)trailing-edge.com Trailing Edge Technology WWW: http://www.trailing-edge.com/ 7328 Bradley Blvd Voice: 301-767-5917 Bethesda, MD, USA 20817 Fax: 301-767-5927

26 years, 10 months

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CS/80

by gossonb＠kan.marconi.ca

I don't know if you are still interest in any of this stuff but I have copies of the CS/80 protocol. I actually support a system that was development in the early 80's and is still in use by British Telecom. We have prototype and are putting together a proposal to use a PC with a GPIB card to emulate a disk drive using the CS/80 command set. Let me know if you have any interest in this. Regards, Bruce Gosson Braddan Bridge Consulting bgosson(a)cyberus.ca

26 years, 10 months

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Damn fools (was Re: Dell "Oldest PC" winner on dent)

by ccfsm＠ipa.net

This has been an interesting, uh, exchange of and on many viewpoints and I've found value in quite a bit of it, i.e. it makes you think. But I do take exception to >> Even business do things they don't like or wish to do. Businesses, just like the independent people who run them, can only do what they want to do. You do what you want to do - always. You might hide your decisions behind the guise of "business made me do it" or "my spouse won't let me keep the 5360 in the house" or some such, but you made the decision, your choice is your choice. Businesses both big and small hide behind this "we didn't want to do it" nonsense as do individuals - but you can only do what it is you indented to do, what you want to do, unless of course you have a dirty bus connector or a bad memory module or a flaky CPU or faulty programming, eh? You list the possible decisions, the possible outcomes of each decision, the relative plus and minus of each variable - and then you decide what course of action to take, You do what you want. BTW - Does anybody know of any hobby level (cheep) GP-IB programming tools? All I want to do is control several DVM and a counter and function generator - minimal stuff for very basic bench automation. Any ideals? Thanks Roger Goswick Coca-Cola Bottling rdg

26 years, 10 months

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Fwd: Commadores and IBM available in Cleveland Ohio

by dlw＠trailingedge.com

A non-text attachment was scrubbed... Name: not available Type: text/enriched Size: 1256 bytes Desc: not available Url : http://www.classiccmp.org/pipermail/cctalk/attachments/19990826/77ea6430/at…

26 years, 10 months

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Wes Graham Obit

by cdrmool＠interlog.com

26 years, 10 months

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Fwd: Re: Comments? Proper way to (un)subscribe CLASSICCMP

by allisonp＠world.std.com

included are the headers as I typically get them. RDFmail collects the whole mess from SGI unix (or whatever they call it) via mail. Allison <From CLASSICCMP-owner(a)u.washington.edu Wed Aug 25 21:51:24 1999 <Return-Path: <CLASSICCMP-owner(a)u.washington.edu> <Received: from lists3.u.washington.edu (root(a)lists3.u.washington.edu [140.1 < by world.std.com (8.9.3/8.9.3) with ESMTP id VAA16032; < Wed, 25 Aug 1999 21:49:39 -0400 (EDT) <Received: from host (server(a)lists.u.washington.edu [140.142.56.13]) < by lists3.u.washington.edu (8.9.3+UW99.02/8.9.3+UW99.01) with SMTP id SAA0 < Wed, 25 Aug 1999 18:49:04 -0700 <Received: from mxu4.u.washington.edu (mxu4.u.washington.edu [140.142.33.8] < by lists.u.washington.edu (8.9.3+UW99.02/8.9.3+UW99.01) with ESMTP id SAA3 < for <classiccmp(a)lists.u.washington.edu>; Wed, 25 Aug 1999 18:48:57 -0700 <Received: from quartz.netsync.net (IDENT:root@quartz.netsync.net [206.231.8 < by mxu4.u.washington.edu (8.9.3+UW99.02/8.9.3+UW99.08) with ESMTP id SAA27 < for <classiccmp(a)u.washington.edu>; Wed, 25 Aug 1999 18:48:56 -0700 <Received: from default (jmtnppp191.netsync.net [208.20.32.205]) < by quartz.netsync.net (8.9.3/8.9.3) with SMTP id VAA02554 < for <classiccmp(a)u.washington.edu>; Wed, 25 Aug 1999 21:37:06 -0400 <Message-Id: <4.1.19990825213253.00a82460(a)206.231.8.2> <Date: Wed, 25 Aug 1999 21:48:41 -0400 <Reply-To: classiccmp(a)u.washington.edu <Sender: CLASSICCMP-owner(a)u.washington.edu <Precedence: bulk <List-Help: <http://www.washington.edu/computing/listproc/> <List-Unsubscribe: <mailto:listproc@u.washington.edu?body=unsubscribe%20clas <List-Subscribe: <mailto:listproc@u.washington.edu?body=subscribe%20classicc <List-Owner: <mailto:classiccmp-request@u.washington.edu> (Human contact for <List-Post: <mailto:classiccmp@u.washington.edu> <From: Christian Fandt <cfandt(a)netsync.net> <To: "Discussion re-collecting of classic computers" <classiccmp(a)u.washingto <Subject: Re: Fwd: Re: Comments? Proper way to (un)subscribe CLASSICCMP <In-Reply-To: <Pine.GSO.4.05.9908221207410.8085-100000@shell1> <References: <4.1.19990821214656.00a99100(a)206.231.8.2> <Mime-Version: 1.0 <Content-Type: text/plain; charset="us-ascii" <X-Sender: cfandt(a)206.231.8.2 <X-Listprocessor-Version: 8.1 -- ListProcessor(tm) by CREN <Status: R < <Upon the date 12:08 PM 8/22/99 -0700, Sellam Ismail said something like: <>On Sat, 21 Aug 1999, Christian Fandt wrote: <> <>> Is it true that Jon and some others do not get a type of header containi <>> all the info such others of us do? Such as the following FWD'ed piece o <>> Sellam's msg: <> <>Wow, I've never seen that stuff. Does that appear for every message you <>read in your mailer software? It's probably in the headers, but PINE <>doesn't display it for me. < <Hi Sellam, < <Just got back from a mini vacation down to Dayton, Oh. (That Air Force <Museum just gets better and better . . . :) So, I'm just getting into a <stack of 448 messages piled up since Sunday AM. < <Yes, it does appear for every msg from ClassicCmp. Those five lines just <suddenly started to be included with the header one day and that day _may_ <IIRC, have coincided with the new list server software Derek mentioned tha <the U. of Wash. installed. < <Here's the five extra header lines copied again for those who weren't <keeping track of the thread early on: < <"List-Help: <http://www.washington.edu/computing/listproc/> <List-Unsubscribe: <<mailto:listproc@u.washington.edu?body=unsubscribe%20classiccmp> <List-Subscribe: <<mailto:listproc@u.washington.edu?body=subscribe%20classiccmp%20YourName> <List-Owner: <mailto:classiccmp-request@u.washington.edu> (Human contact fo <the list) <List-Post: <mailto:classiccmp@u.washington.edu>" < <I haven't ever used PINE but I understand it is a text only email program <(which is what we only need 99.95% of the time.) So, perhaps there's some <funny stuff going on with the formatting of the text and PINE just happily <ignores it. With Eudora Pro, for example, those URLs are underlined links <and all I have to do is click on one if I need to use that function. Sort <of handy I think, but it does add to the length of the msg file. < <I suppose Derek may have weighed-in already with his expert input on the <list s/w, so I'd better shut up now. (Hey, he's a student and keeper of <this list at the U. of Washington, so that makes hime the de facto "expert" < <Regards, Chris <-- -- <Christian Fandt, Electronic/Electrical Historian <Jamestown, NY USA cfandt(a)netsync.net < Member of Antique Wireless Association < URL: http://www.antiquewireless.org/ <

26 years, 10 months

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VAXstation 3100/30 Questions

by allisonp＠world.std.com

<4MB on the motherboard and two daughter boards with 12MB and <8MB. The two daughter boards connect together with only one <connecting to the motherboard. Where would you attach another <board with 8MB more memory? You don't. You use a 16mb card. They were configured in different sizes. For a VAX 8-16mb (pre1990) was a LOT of memory and VMS (or ultrix) typically ran very well in that. I have a 3100m10e with 24mb (1x16 +1x8). The other thing is not all 3100s used the same scheme for mounting memory. My 3100/m76 uses a version of 72pin simms (it was a later machine). <Although the system came with a hard drive and OpenVMS, I got the <hobbyist OpenVMS CD-ROM and want to install it on another hard <drive that I've added. The drive is an IBM Model 0663-H, which <is a 1GB (slightly less, actually, if you count in base 2) drive. <The specs for the drive say it is "compatible" with the VS3100 <when a configuration is made using a SCSI command (which I have <no way of doing, of course--it must be done by a driver). I <connect the drive, the VS3100 console sees it fine, and then I <try to do a low-level format using Test 75. At various times <(varies randomly) into the formatting progress I get an error <"PV_SCS_FMT_ERR#2", which I have no idea of its meaning. What <does this mean? I though test 71 is the righ one. Also you have to have the correct SCSI address (anything but 6, thats the vax). Also most of the 3100s have two scsi busses with disks as DKAnnn, or DKBnnn. <Is there any termination on the internal SCSI A bus on this <machine, or does the last drive on the cable need to do it? <(The IBM Model 0633-H doesn't have any, and it was on the <middle connector.) I believe SCSI A is self terminating if the cable forms a loop. If the MV3100 has a different SCSI scheme you may need to terminate. Also SCSI B on all of mine needs termination. I've used non DEC drives successfully. Thought he CDrom can be installed comfortably on a single RZ56 (680mb) and VMS will fit on much smaller. I've just done my first 7.2 install on my M10e, the base system with everything used less than 300k blocks (150mb). Allison

26 years, 10 months

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First Book of KIM

by rcini＠msn.com

Hello, all: Last night, I sort of got approval from Jim Butterfield to post a copy of The First Book of KIM. He really didn't say "do it", but he said to look at this other guy's work and look at the copyright in the book (it's really an anti-copyright). First off, here's a useful URL http://www.total.net/~yhpun/Kim-1.html Second, I'll more than likely start scanning the book next week, to eventually be posted on the secure area. Rich ----------------------------------- [ Rich Cini/WUGNET [ ClubWin!/CW7 [ MCP Windows 95/Windows Networking [ Collector of "classic" computers [ http://highgate.comm.sfu.ca/~rcini/classiccmp/ <---------------------------- reply separator

26 years, 10 months

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More mailing list spam

by kyrrin＠bluefeathertech.com

The recent 'Color TV' spam has been traced and identified, and a formal complaint has been filed. If anyone else wishes to express their displeasure, please feel free to send your comments (preferably polite) to: prion(a)diginet.net (He's listed as the administrative contact for the domain ELIPIA.CO.KR, who is hosting KOTEC.NET -- the domain that spammed us). tychoi(a)samsung.co.kr (Listed as the domain contact for unitel.co.kr, where the spammer(s) are maintaining a mailbox). Enjoy, but remember... one catches a lot more flies with honey than vinegar. -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Bruce Lane, Owner and head honcho, Blue Feather Technologies http://www.bluefeathertech.com // E-mail: kyrrin(a)bluefeathertech.com Amateur Radio: WD6EOS since Dec. '77 "Our science can only describe an object, event, or living thing in our own human terms. It cannot, in any way, define any of them..."

26 years, 10 months

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Fwd: Re: Comments? Proper way to (un)subscribe CLASSICCMP

by cfandt＠netsync.net

Is it true that Jon and some others do not get a type of header containing all the info such others of us do? Such as the following FWD'ed piece of Sellam's msg: >Date: Sat, 21 Aug 1999 10:54:17 -0700 (PDT) >Reply-To: classiccmp(a)u.washington.edu >Sender: CLASSICCMP-owner(a)u.washington.edu >List-Help: <http://www.washington.edu/computing/listproc/> >List-Unsubscribe: <mailto:listproc@u.washington.edu?body=unsubscribe%20classiccmp> >List-Subscribe: <mailto:listproc@u.washington.edu?body=subscribe%20classiccmp%20YourName> >List-Owner: <mailto:classiccmp-request@u.washington.edu> (Human contact for the list) >List-Post: <mailto:classiccmp@u.washington.edu> >From: Sellam Ismail <dastar(a)ncal.verio.com> >To: "Discussion re-collecting of classic computers" ><classiccmp(a)u.washington.edu> >Subject: Re: Comments? Proper way to (un)subscribe CLASSICCMP >X-To: Discussion re-collecting of classic computers ><classiccmp(a)u.washington.edu> >X-Authentication-Warning: shell1. ncal.verio.com: dastar owned process doing >-bs > >On Sat, 21 Aug 1999, Jon wrote: > >> Can someone refresh my memory as to the proper procedure to subscribe >> & unsubscribe from this list? > >I'll just post this publicly: > >send e-mail to listproc(a)u.washington.edu -- snip -- May be the reason Jon had no info at hand how to unsubscribe . . . Regards, Chris -- -- Christian Fandt, Electronic/Electrical Historian Jamestown, NY USA cfandt(a)netsync.net Member of Antique Wireless Association URL: http://www.antiquewireless.org/

26 years, 10 months

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Portable color TV

by swcl＠unitel.co.kr

We SOWON, are one of the leading designers of quality portable color TV receiver employing state of the art microprocessor technology in Korea. SOWON has long been experienced and involved in the electronics industry, which now leads the current wave of changes, supplying a broadcast receiving equipment since it,s inception. Since then, we have diversified our business on high expectations that international trade will be more important in the 21st century, thus helping to build a more affluent society. With the aim of improving the quality of life and proposing a new sense of value, SOWON will exert every endeavors to fulfill your requirement whenever you want something special. Whether you're in work or in leisure, our quality product can be with you! home page: http://www.swn.co.kr Tel: 82-2-2249-4311 Fax: 82-2-2242-3693 E-mail: swcl(a)unitel.co.kr For more details at our website.

26 years, 10 months

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Wanted: jumper settings for Teac FD-235HF-101

by ethan_dicks＠yahoo.com

--- Tony Duell <ard(a)p850ug1.demon.co.uk> wrote: > This is not typical. Most older FDC cards drive all the floppy interface > lines with 7438 (or similar open-collector gates) devices. More modern > ones put everything into the same ASIC as the floppy controller logic > (and maybe other things as well). Right. The Amiga is atypical. This PeeCeeoid is industry standard inside. > > I'm trying to make a cable to hook up floppy drive to a proprietary DB-25 > > external connector on a sealed PeeCeeoid. > > Sealed? No such thing :-)... That's what screwdrivers, torx drivers, > hammers, etc are for.. Of course. That's how I got as far as I did - I disassembled the box, located a 34-pad spot on the motherboard where a floppy connector *should* go, then used a VOM to trace the wiring between the internal 34-pin connector and the external 25-pin connector. What stumped me was a lack of /MOTORON (pin 16). All is now well. It boots Linux just fine. Thanks. -ethan === Infinet has been sold. The domain is going away. Please send all replies to erd(a)iname.com __________________________________________________ Do You Yahoo!? Bid and sell for free at http://auctions.yahoo.com

26 years, 10 months

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RK11 and M9312 questions

by wrking＠tsoft.com

I just received a load of boards that were associated with an 11/34. I'm going to try to upgrade my 11/04, but since I don't have any doc's I have a few questions. If anyone could help, it would be greatly appreciated. 1. What are the switch settings for a M9312 bootstrap/terminator card? 2. On the M9312, there is a jumper that has been lifted on the left edge of the card (next to the third chip up from the edge connector). What's this for? 3. My M9312 has three empty sockets. Is this normal? 4. I have a 4 board set for the RK11 controller. Can this plug into a standard unibus, or does it require a special backplane? If I remember correctly, you use a unibus extension cable to daisy chain into the rk05's. 5. Can anyone direct me to the description of the two edge connectors on the top of the 11/34 board set? Thanks, Bill

26 years, 10 months

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xxdp boot disk

by jritorto＠nut.net

how do I make a bootable rx33 xxdp disk? I currently have version 2.5 on an rl02. TIA jake

26 years, 10 months

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Wanted: jumper settings for Teac FD-235HF-101

by ethan_dicks＠yahoo.com

--- Tony Duell <ard(a)p850ug1.demon.co.uk> wrote: > > > Silly suggestion. Have you tried linking pin 16 on the drive to the drive > > > select line (pin 14 most likely). Leave the drive select wire connected > > > there as well. So that the motor goes on whenever the drive is selected. Based on the depth of the ongoing discussion, I gave this a try. I works! > In any case, blowing a transistor is a lot less of a problem than blowing > a custom chip. The transistor is on the Amiga (which I was using for schematic examples); this drive is going on bizzaro PC device. > I've forgotten what you're trying to do, but what happens if you just > match up signal names as above? I'm trying to make a cable to hook up floppy drive to a proprietary DB-25 external connector on a sealed PeeCeeoid. Thanks for the help! -ethan === Infinet has been sold. The domain is going away. Please send all replies to erd(a)iname.com __________________________________________________ Do You Yahoo!? Bid and sell for free at http://auctions.yahoo.com

26 years, 10 months

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Speaking of Tandys... 2800HD parts?

by musicman38＠mindspring.com

-----Original Message----- From: musicman38(a)mindspring.com <musicman38(a)mindspring.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Wednesday, August 25, 1999 11:48 AM Subject: Re: Speaking of Tandys... 2800HD parts? >>I just picked up a Tandy 2800HD laptop! Anyone have any clues/leads where >>I can find a power supply board and floppy drive for this thing? >> > > >You can still buy a new one from Tandy. See Tandy.com >or you can build one, I think its 9.8 volts.. >But you can goto their support site and it will give you the specs on it.. > >I purchased mine form them as it need one also, about $16.00 I think.. > >Phil... > Correction the website is http://support.tandy.com/ Phil...

26 years, 10 months

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Damn fools (was Re: Dell "Oldest PC" winner on zdnet)

by Philip.Belben＠pgen.com

> Well, archeology was, and still _is_ about value, and I'm not > talking about anything beside money. Just look at your news. > If theres a stupid pile of roman silver, it's top news and > it gets a lot of attention. The historic value is zero, but > it's silver - on the other side, it needs a earth shaking > discovery (like the Keltic statue two years ago) just to > have a few lines... Non sequitur, I think. I agree that the news coverage bears this out well, but I don't agree that this is the opinion of _any_ serious archaeologist, amateur or professional, of my acquaintance. I think that news coverage is about money. The money mentality that pervades so much of our society means that the newspapers measure the importance of _anything_ they don't actually understand by the amount of money involved. Money is as relevant to archaeologists as it is to the rest of us, but I don't think it is the main driver for most, or even many, of the people who do significant work in this field. Philip. PS I don't recall hearing about this Celtic statue - can you point me to more detail?

26 years, 10 months

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Speaking of Tandys... 2800HD parts?

by musicman38＠mindspring.com

>I just picked up a Tandy 2800HD laptop! Anyone have any clues/leads where >I can find a power supply board and floppy drive for this thing? > You can still buy a new one from Tandy. See Tandy.com or you can build one, I think its 9.8 volts.. But you can goto their support site and it will give you the specs on it.. I purchased mine form them as it need one also, about $16.00 I think.. Phil...

26 years, 10 months

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