<PDP-11 is certainly doable in the 4010 part, but I don't know if I could d <it and the 11/70 MMU or if I'd end up using two parts. These parts are Definately two or more to do 11/70 or the J11 (similar) as the MMU is a lot of registers (memory cells) and the CPU is not short on them either. <"slow" (50Mhz) which is a hell of a lot faster than a lot of -11's :-) In reality when you get the end of the design you find the interconnect delays internal to the chips will have you far slower. The J11 run with something like a 16 mhz clock for the early parts and the crop in the 11/93 I'd guess are closer or faster than 30mhz. <> What architecture? Microcoded or gates? Microcode requires an <> assembler, but might be quicker in the long run. < <Intel sued several people over the alleged use of Pentium microcode, <legally gates would probably be safer, also microcode == memory and memory <eats gates rapidly (even though the Xilinx have some cool features to avoi <that) and intel lost to nec as V20 microcode was actually wider! Microcode would be in external EEproms or some such to get the wide words needed to make the cpu fast. <Sounds like the definition of a hobby to me. :-) I'm going to do a PDP-8 o <my evaluation board, and after that will look at helping out on a PDP-11. Better place to start. The PDP-8 is not register intensive nor does it have many states that make sequential logic complex. The -8 has three 12 bit register and may be a temp (PC, MQ, ACC and MA(a temp)). The base PDP-11 (11/20, LSI11, T11) has 8 16bit registers plus flags and maybe temps for internal use. See why PDP-11 is more complex for FPGA? The base 11 has nearly 18bytes of ram never minding other flipflops needed! Hope this makes it more sense of the scale of complexity. The PDP-11 is the most CISC of the 16bitters and is only exceeded by the VAX. Allison