Never mind, I just realised there was a little "+" sign well away from the
symbol that allowed me to select it. It looks like the symbol is somehow
much bigger that how I have drawn it. I should be able to work it out now.
Regards
Rob
From: Rob Jarratt <robert.jarratt at ntlworld.com>
Sent: 07 March 2020 17:12
To: General Discussion: On-Topic and Off-Topic Posts (cctalk at classiccmp.org)
<cctalk at classiccmp.org>
Subject: Can't Select a Custom Device in Eagle
I have been using Eagle to reverse engineer a PSU schematic. I decided I
needed to make a custom device in Eagle for the transformer. I have done
this and it seems to be fine, except that when I put the symbol on a
schematic, after I have confirmed its position, I can't select it, so I
can't move it or anything.
I have done some web searches but I can't find anything about this. Anyone
know what the problem might be?
I am using the free version, and I am on version 7.2.0. Looks like later
versions are subscription only and I am reluctant to do that because they
could take away access at any time.
Thanks
Rob
I have been using Eagle to reverse engineer a PSU schematic. I decided I
needed to make a custom device in Eagle for the transformer. I have done
this and it seems to be fine, except that when I put the symbol on a
schematic, after I have confirmed its position, I can't select it, so I
can't move it or anything.
I have done some web searches but I can't find anything about this. Anyone
know what the problem might be?
I am using the free version, and I am on version 7.2.0. Looks like later
versions are subscription only and I am reluctant to do that because they
could take away access at any time.
Thanks
Rob
Hopefully collective wisdom can help on this one - does anyone have a clue
what system this core board was from:
http://www.classiccmp.org/acornia/tmp/coresmall.jpg
The curved edge connectors (presumably to make board insertion easier) are
quite distinctive, plus the way the power's fed in via an edge connector on
the "far" side of the board. What's interesting to me is the core ring
size; the TTL ICs on the board have 1970 date codes, but I didn't think
that the rings got quite that small until right at the end of core's era,
more toward the end of the decade.
It seems to be 8 blocks of 64x64, i.e. 4KB. p/n on the main board of
2001000755, and just hidden from view under the core daughterboard is a
logo that says "LEC", which I suppose might be meaningful.
There's a bigger (2181x1863) image as "coreboard.jpg" in the same dir if
more detail helps (I doubt it), but it's 2.4MB so maybe save Jay's
bandwidth by only looking at that one if you absolutely have to :-)
thanks,
Jules
> On Mar 5, 2020, at 05:20, Plamen Mihaylov via cctech <cctech at classiccmp.org> wrote:
>
> ? Does anyone have such machine ? I miss the PSU adapter as well as the Sbus
> framebuffer which connects the LCD panel to the mainboard. Any info is
> appreciated.
I had one, but sold it to someone on this list last year.
I used a generic power supply, one with multiple cord tips and selectable output. However, when I exhibited the BriteLite and had it running all day, the power supply died after a day and a half.
Good luck on finding a frame buffer for it. I don?t remember the details about it, but I took lots of photos of it.
alan
>
> Best regards,
> Plamen
> Date: Thu, 5 Mar 2020 14:23:30 +0200
> From: Plamen Mihaylov <plamenspam at afterpeople.com>
> Subject: RDI BriteLite
>
> Does anyone have such machine ? I miss the PSU adapter as well as the Sbus
> framebuffer which connects the LCD panel to the mainboard. Any info is
> appreciated.
>
> Best regards,
> Plamen
>
I have several BriteLites, including IPC, IPX, and LX versions.
I will see what power supplies go with them.
The Sbus video board is something special for the LCD panel.
--
Michael Thompson
Looking at the datasheet for the 6809 (specifically, the 6809E that
needs incoming quadrature clock), I read that !HALT can be asserted
200nS (for 1MHz part) before falling Q and the CPU will finish the
existing instruction and then go into a HALT state as long as the HALT
line is low during the falling edge of Q.
That's the store from the datasheet, but when I am testing it, I see
that, even if I pull HALT low at the very beginning of the last cycle of
an instruction, the 6809 will not acknowledge the HALT until executing
the next instruction.
My logic is watching for IO address $ff61.? When found, it drops Q
so, to start the HALT condition, I need only:
lda $ff61
Not that the trigger is being performed by the code, so the current
instruction (the lda) should complete and then the CPU should go into
HiZ.? What I see is:
lda $ff61
lda $ff60 <- the next instruction
executed, and THEN the CPU goes into HiZ.
I can deal with this (Yes, I should just look at BS=BA=1, which tell
when to safely use the bus, but I don't have access to those signals for
this project), but I thought I'd see if this was known by all, or if
there is something I am missing.
Jim
--
Jim Brain
brain at jbrain.comwww.jbrain.com
