addressing only the comment quoted below . . .
Really, Tony, I think you overemphasize the importance of the individual
user to the semiconductor manufacturers. The level of competition for the
FPGA business has escalated to where the development software, previously
costing several K-bucks US, now costs as little as $100, and, in the case of
ALTERA, is quite free. Now, that's not the complete package with all the
bells and whistles, but it's enough to build a device from start to finish.
I really doubt that it would turn out to be illegal to take the old 11-70 or
whatever schematic and essentially clone it in an FPGA, but I doubt a clever
rebuilder would want to do that anyway. It might be either equally good in
the end product to build the thing so it's thriftier than the TTL design
would be, yet still a bit faster, or so it's quite a bit faster and perhaps
not quite the same. It doesn't have to be identical to run the same code.
The technology in FPGA's these days is such that it enables devices to
operate between 10 and 50 times the speed of the old TTL logic designed in
the '70's. That doesn't mean you can take a '70's design and
"transliterate" it and make it run lots faster, though that is conceivable.
What it does mean is, similarly to translating poetry from one language to
another, logical constructs can be ported from one technology to the other,
changing the outward and physical details of the circuitry, yet preserving
the upper-level sense of the logic in such a way that it capitalizes on the
available enhancements, thereby yielding a product which is quite different
>from the original, yet performs the identical task in more or less the same
way at MUCH greater speed, or MUCH lower complexity, and, hopefully lower
cost.
Once you've translated a poem, you've done the same work as the poet, more,
in fact, yet you've created nothing new. OTOH, in the case of the computer,
redesigned to capitalize on new technology, I believe you could argue that
it is, indeed, something quite new. If it were to be generated for, say , a
XILINX part of the 5200 series, it would not necessarily be very costly, nor
would it be difficult once one has the original print set as crib sheets.
What's more, it would potentially be so much faster than the original, and
take up so much less space, e.g. a 2" square package, you could build the
MMU into it and interface it directly to the DRAMs, maybe adding a circuit
to copy the ROM code into RAM during its boot.
Schematic entry would be the easiest way to clone the prints, but HDL is
considered by many to be the best way to implement an architecture, the
behavior of which is well defined and understood. If you build your device
in VHDL or VERILOG, it is inherently portable, since both XILINX and Altera,
among others, support both.
Building a device like this in several parts merely ups the cost, since
resources are consumed by the interconnection between them. Time is used up
in the interconnections as well, so performance would be lower. When all is
said and done, the single FPGA is the "right" notion.
I don't think the FPGA makers would care if you use their parts to craft a
device. If you have the HDL code, nearly any distributor will provide you
access to the resources to implement it in a product they sell, provided you
buy the parts from them. They cost a few dollars in small quantity, but if
you say the right "things" when approaching them, and seem sufficiently
eccentric, they'll treat you right.
Dick
-----Original Message-----
From: Tony Duell <ard(a)p850ug1.demon.co.uk>
To: Discussion re-collecting of classic computers
<classiccmp(a)u.washington.edu>
Date: Thursday, August 26, 1999 4:08 PM
Subject: Re: PDP era and a question
<snip>
>I am sure it's illegal to (say) take the PDP11/70 printset, modify it so
>that it could work in an FPGA (and there would be significant mods), and
>implement it like that. I am not so sure there would be any problem if
>you just took the instruction set and designed a CPU to run it without
>using any DEC printsets. People have done this with the PDP8 for many
years.
>
>
>>
>> Given the complexity of the 11/70 CPU it should be possible to put the
>> entire thing inside a relatively inexpensive FPGA these days. Given
>> something like NetBSD that is already multi-architecture aware, that
would
>> make it possible to have an open source OS running on it. We could
>> potentially get to a system that was completely "open hardware." (ie
anyone
>> could build one with no royalty requirements, and hackers could build
them
>> for fun.)
>
>If you wanted to do this, then it would probably be easier to design a
>CPU from scratch (which is not hard) that was better suited to running
*BSD.
>
>Also, be warned that if you're going to use FPGAs you have to use the
>manufacturer's tools which are not going to be Open-Source, and which are
>not going to run under Open-Source OSes. Several of us have moaned about
>this for quite a time, but alas there are no 100% documented FPGAs out
>there, and if anyone manages to crack the configuration format, you can
>bet the manufacturers will change it, along with a 'free update' to the
>official tools.
>
>In other words, the machine won't really be free for anyone to construct.
>
>-tony
>
< How many gates is a single chip processor going to use? And how
< expensive is an FPGA that size. Or are large PALs a better choice
< (free tools for AMD/Vantis MACH series, and Altera's entry level
< parts)
Figure well in to the 10000+ region. The PDP-11 looks simple but it's
not!
< What to use for a system. If I use a QBus based system (I have
< several available) what are the timing requirements? Is there
< a doc for this? Or Unibus? Or (my current favorite) Socket-7...
Least significant consideration. First the chip/chips.
< What architecture? Microcoded or gates? Microcode requires an
< assembler, but might be quicker in the long run.
Microcoded, all of the chip level 11s are (LSI-11, F11, T11, J11).
< And when its all done, what is it really good for? How many
< "hardware hackers" are interested in building CPU boards, and
< are willing to share the cost of laying out and manufacturing
< PCBs?
Look a any PDP-11 ask that question, theres your answer.
<I will probably make a stab at it, but depending on life, might not
<ever finish...
It's doable, the docs needed are commonly available. Costly.
Allison
><http://www.newscientist.com/nsplus/insight/ai/primordial.html>
Wow, thanks for that link, John. I was not aware that this type of 'genetic
programming' had actually come this far. The one thing that bothers me about
it is that the scientist does not know how it works. Although I realize that
it has to come to this at some point, I would really like to know how the
machines which I create function. Besides for the fact that I would then be
able to fix them, I could also rule out the possibility of this machine
trying to take over the world or some such thing (possible with an advanced
enough machine).
The rule of thumb back in the '70's was that TTL was "good" to 25 MHz.
Current generation FPGA's routinely operate at 10x that speed, while, in
reality, it was an exceptional TTL design of the '70's that would allow a
significant bit of circuitry, e.g. a FIFO or a synchronous state machine, to
operate across more than a very few bits at that speed. Typical prop-delays
of 10-15 ns would add up quickly. (remember that we've since then learned
about pipleine registers, which were not in common usage then.)
The latest (e.g. VIRTEX) families boast synchronous performances of 500 MHz
for such structures, though their CLB's (configurable logic blocks) have
prop-delays of under a ns and clock-to-q prop's in that range as well.
Those CLB's are really lookup tables in which you program a random function
of up to 5 variables, hence get the same prop whether it's a nand or an
xnor.
It would take a clever designer indeed to get anywhere near the top level of
performance with a rework of the PDP-11 processor, but it's been attempted.
There are more than one of them out there, though I haven't kept up on that.
Nevertheless, if you do it, particularly in a popular HDL, you're developing
essentially your own intellectual property, and in a portable medium which
you can use with any vendor's product.
Dick
-----Original Message-----
From: allisonp(a)world.std.com <allisonp(a)world.std.com>
To: Discussion re-collecting of classic computers
<classiccmp(a)u.washington.edu>
Date: Friday, August 27, 1999 6:35 AM
Subject: Re: PDP era and a question
>> The technology in FPGA's these days is such that it enables devices to
>> operate between 10 and 50 times the speed of the old TTL logic designed
in
>
>Old ttl was nowhere near that much slower. The lowly 7400 in 72 was
>comfortablly under 15ns, true the FPA part may be under 1ns now but...
>that's not 50X! Of course adding interconnection delays and other factors
>the 10x number is very honest.
>
>> the '70's. That doesn't mean you can take a '70's design and
>> "transliterate" it and make it run lots faster, though that is
conceivable.
>
>This is true of any from one logic system to another. PDP-8 for example
>used a lot of "wired or" and similar logic in the data paths to conserve
>gates. Of course that was a slower way to do it but lower cost too.
>So a design translation can buy speed at the cost of logic or design
>effort.
>
>> Schematic entry would be the easiest way to clone the prints, but HDL is
>> considered by many to be the best way to implement an architecture, the
>> behavior of which is well defined and understood. If you build your
device
>> in VHDL or VERILOG, it is inherently portable, since both XILINX and
Altera,
>> among others, support both.
>
>VHDL is the way to go but developing the description would be the real
>work.
>
>> access to the resources to implement it in a product they sell, provided
you
>> buy the parts from them. They cost a few dollars in small quantity, but
if
>> you say the right "things" when approaching them, and seem sufficiently
>> eccentric, they'll treat you right.
>
>Roger that. Besides, they know if you do one your likely to use it for
>other things (drag factor).
>
>Allison
>
Can someone help this guy out? Please reply to the original sender.
Reply-to: garald4(a)net-link.net
---------- Forwarded message ----------
Date: Thu, 26 Aug 1999 18:10:01 -0700
From: Garald Austin Barton IV <garald4(a)net-link.net>
To: vcf(a)vintage.org
Subject: Harris Mainframe?
I am a college student looking for information about a mainframe.
Harris (Data Communications Division)
Model No. KH174-32R
Made approx. 1984
Thank you for your time. Any response is appreciated.
garald4
Sellam Alternate e-mail: dastar(a)verio.com
-------------------------------------------------------------------------------
Puttin' the smack down on the man!
Coming this October 2-3: Vintage Computer Festival 3.0!
See http://www.vintage.org/vcf for details
[Last web site update: 08/17/99]
[Last web site update: 08/17/99]
>Other companies have made drop-in PDP-11 replacements over the years, too.
>QEI (based in MA) makes drop-in upgrades for 11/34's, 11/44's, and
>11/70's, and Setasi (in Florida) makes drop-in upgrades for 11/70's.
Correction it is QED in MA. I have one of their J11 upgrades for 11/24's - with
docs.
QEI is a DEC dealer.
There is also Nissho that I have seen info on but have never played with.
>Yes, I have run RT-11, RSX-11, and 2.11 BSD on systems that didn't
>have a single DEC hardware component in them. (For example, a Mentec
>M100 CPU and Andromeda disk controller in a third-party Q-bus backplane.)
>
The M100 I have in hand still uses the J11 however. I think the latest ones
they went away from real J11's.
Dan
>Making a processor is not hard (although FPGAs might make it harder than
>just using simple TTL chips -- some of the manufacturer's claims on this
>are plain false). I'd not try to re-implement the PDP11 unless you had a
>good reason to do that -- rather, design an instruction set and
>architecture and implement it.
I agree 100% here. *Especially* if your goal is to run NetBSD or Linux
or (insert popular Unix-like free OS here). These OS's simply don't
fit well into the 16-bit virtual address space of an -11 (2.11 BSD
has many of the features of modern Unices, but doesn't have the wastage
found in NetBSD or Linux).
A small, RISC-ish instruction set is perfect for implementing NetBSD
on. Things get a bit more complicated as you add the necessary memory
management, of course!
--
Tim Shoppa Email: shoppa(a)trailing-edge.com
Trailing Edge Technology WWW: http://www.trailing-edge.com/
7328 Bradley Blvd Voice: 301-767-5917
Bethesda, MD, USA 20817 Fax: 301-767-5927
<are plain false). I'd not try to re-implement the PDP11 unless you had a
<good reason to do that -- rather, design an instruction set and
<architecture and implement it.
Good point. If you want a good -11, find one. Myself I find the 11
to be more of a software playground with that instruction set.
If I were doing my own, well then, it's a matter of what if...
I'd start with a 32bit PDP-8 (just add 20 more bits on the right side).
I'd keep the PDP-8 instructions (add a few more microcoded ones for byte
ops), addressing and IO. With 32bit addressing and 27 bits direct
addressing in both current page and page 0 it would make a good enough
graphics cpu to be useful, if fast. Even if scaled back to 24 bits it
would be interesting. Also very buildable using 74F parts. At the same
time old PDP-8 code could be "lofted" to run on it so a OS would be
possible in a reasonable time. With a little effort a .3us instruction
cycle is very doable (3mips!) maybe even faster. Pentium no, but fast
enough to make some sense.
Allison
As was pointed out on the NetBSD list, Compaq has officially End-of-lifed
(EOLd) the VAX architecture. This follows a trend of having EOLs the -8,
-10, -11, and now VAX series.
I suggested to some folks, off list, that perhaps DEC should make the
PDP-11 architecture "open source" in the sense of allowing anyone to
produce PDP-11 capable processors but was told that Mentec has purchased
the rights to the PDP-11 architecture from DEC. What's up with that? True?
False? Kind-a true? (I know Mentec sells PDP-11 compatible computers)
Given the complexity of the 11/70 CPU it should be possible to put the
entire thing inside a relatively inexpensive FPGA these days. Given
something like NetBSD that is already multi-architecture aware, that would
make it possible to have an open source OS running on it. We could
potentially get to a system that was completely "open hardware." (ie anyone
could build one with no royalty requirements, and hackers could build them
for fun.)
--Chuck
