12 Mar
2018
12 Mar
'18
7:49 a.m.
As the most obvious example of the impedance mismatch between 370
architecture and 68000 microarchitecture, the 68000 is hardwired to have
eight each data and address registers, not sixteen GPRs, and microcode
can't easily paper over that.
Similarly, the 8087 microarchitecture has hardwired support for binary
floating point normalization, and microcode can't efficiently force that to
do radix 16 normalization.
Both problems could be surmounted (inefficiently) with enough microcode,
but the chips were designed with no significant extra microcode ROM and PLA
capacity.
12 Mar
12 Mar
9:54 a.m.
On 2018-03-12 15:49, Eric Smith via cctalk wrote:
As the most obvious example of the impedance mismatch
between 370
architecture and 68000 microarchitecture, the 68000 is hardwired to have
eight each data and address registers, not sixteen GPRs, and microcode
can't easily paper over that.
I wouldn't bet on that ...
9:57 a.m.
On Mon, Mar 12, 2018 at 10:54 AM, emanuel stiebler via cctalk <
cctalk at classiccmp.org> wrote:
On 2018-03-12 15:49, Eric Smith via cctalk wrote:
I'm fairly sure of it, based on microarchitectural details in the US
patents on the 68000 design.
As the most obvious example of the impedance
mismatch between 370
architecture and 68000 microarchitecture, the 68000 is hardwired to have
eight each data and address registers, not sixteen GPRs, and microcode
can't easily paper over that.
I wouldn't bet on that ...
10:11 a.m.
On Mar 12, 2018, at 9:57 AM, Eric Smith via cctalk
<cctalk at classiccmp.org> wrote:
On Mon, Mar 12, 2018 at 10:54 AM, emanuel stiebler via cctalk <
cctalk at classiccmp.org> wrote:
I think there was also an article in the IBM Systems Journal when the XT/370
was announced that basically described how this was done and how everything
worked.
TTFN - Guy
On 2018-03-12 15:49, Eric Smith via cctalk
wrote:
I'm fairly sure of it, based on microarchitectural details in the US
patents on the 68000 design. As the most obvious example of the impedance
mismatch between 370
architecture and 68000 microarchitecture, the 68000 is hardwired to have
eight each data and address registers, not sixteen GPRs, and microcode
can't easily paper over that.
I wouldn't bet on that ...
10:41 a.m.
The IBM Systems Journal article does not go into great detail but says
that a complex of three separate processors are used, a modified 68000
that executes "a large subset of 370 instructions", a standard 68000 to
emulate the remainder odf the instructions and a modified 8087 to
execute the floating point.? I am not at liberty to post the document.
Paul.
On 2018-03-12 2:11 PM, Guy Sotomayor Jr via cctalk wrote:
On Mar 12, 2018, at 9:57 AM, Eric Smith via
cctalk <cctalk at classiccmp.org> wrote:
On Mon, Mar 12, 2018 at 10:54 AM, emanuel stiebler via cctalk <
cctalk at classiccmp.org> wrote:
I think there was also an article in the IBM Systems
Journal when the XT/370
was announced that basically described how this was done and how everything
worked.
TTFN - Guy
On 2018-03-12 15:49, Eric Smith via cctalk
wrote:
I'm fairly sure of it, based on microarchitectural details in the US
patents on the 68000 design. As the most obvious example of the impedance
mismatch between 370
architecture and 68000 microarchitecture, the 68000 is hardwired to have
eight each data and address registers, not sixteen GPRs, and microcode
can't easily paper over that.
I wouldn't bet on that ...
10:49 a.m.
On 12 March 2018 at 18:41, Paul Berger via cctalk <cctalk at classiccmp.org> wrote:
I am not at liberty to post the document.
This?
http://ieeexplore.ieee.org/document/5387781/?reload=true
Also:
https://www.researchgate.net/publication/224102395_System370_capability_in_…
If so, it might be this:
https://pdfs.semanticscholar.org/2007/dc1c4e24b021765707191eeef5930b29a69c.…
--
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10:54 a.m.
-----Original Message-----
From: cctalk [mailto:cctalk-bounces at classiccmp.org] On Behalf Of Paul Berger via
cctalk
Sent: Monday, March 12, 2018 1:41 PM
To: Guy Sotomayor Jr via cctalk
Subject: Re: XT/370 microcode
The IBM Systems Journal article does not go into great detail but says
that a complex of three separate processors are used, a modified 68000
that executes "a large subset of 370 instructions", a standard 68000 to
emulate the remainder odf the instructions and a modified 8087 to
execute the floating point. I am not at liberty to post the document.
Paul.
-----
This one? Seems to be freely available.
https://www.researchgate.net/publication/224102395_System370_capability_in_…
-----
paul
9:55 a.m.
On 2018-03-12 15:49, Eric Smith via cctalk wrote:
As the most obvious example of the impedance mismatch
between 370
architecture and 68000 microarchitecture, the 68000 is hardwired to have
eight each data and address registers, not sixteen GPRs, and microcode
can't easily paper over that.
Forgot the smiley:
;-) ;-) ;-)
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