I can't wait to buy one!!! I have a spare Replica-1 just waiting to hook up to a Monster 6502. Just need to wire up a single step switch and this thing will be awesome!!! Cheers, Corey corey cohen u??o? ???o?

Eric had it at the Maker Faire. He'd covered it with a antistatic plexiglass but it still had some static sensitivity. He was exercising it with ( I think ) a R Pi. He'd been depending on the gate capacitance only. I told him that to get it a little more reliable, he would need to increase the capacitance a little for the floating nets. It will cost a little on power but there isn't that high a toggle on all of the nets that are dynamic. 10 to 20 pf should make it more stable. He needed a separate body attachment for the transmission gates. Al he could find were multi transistor packs. Most all of the important buss and status locations have LEDs on them. The layout is close as practical to the original silicon. Dwight ________________________________________ From: cctalk <cctalk-bounces at classiccmp.org> on behalf of Eric Smith <spacewar at gmail.com> Sent: Saturday, May 28, 2016 10:31:39 AM To: General Discussion: On-Topic and Off-Topic Posts Subject: Re: Monster 6502 On Sat, May 28, 2016 at 5:31 AM, Corey Cohen <applecorey at optonline.net> wrote: It doesn't run at full speed. It presently runs in the tens to low hundreds of kHz. If a Replica-1 can be run slower than normal, that might work. Other common 6502-based micros, such as the Apple II or Atari 400/800 will not work at low speed due to inherent timing requirements related to video generation and DRAM refresh. If you wire single-stepping using the RDY line, that should work, though it will only single-step read cycles, not write cycles. You can't single-step the actual clock because it is dynamic logic.

@Eric, All, Light a candle for those in the dark.. If the min. clock speed is dictated by the ability of the gates to hold a charge, as the bits rot away as charge drains (someone said "minimize resistance to ground", but I believe they meant "maximize"?) , then what is limiting the max. clock speed? Is it just basic PCB stuff, like trace inductance, mutual / parasitic capacitance, etc? Or are there other, more critical factors? I can't imagine propagation delays could matter at these slow speeds.. requiring meandering of traces and so forth. On Sat, May 28, 2016 at 2:55 PM, Corey Cohen <applecorey at optonline.net> wrote:

On 2016-May-28, at 6:22 PM, drlegendre . wrote: Yes, they're talking FET gates, the internal registers would operate under the same basic principle as DRAM does. Other early microprocs used dynamic registers, I forget which, perhaps others can list them. Far from the first time a processor had dynamic registers. I've been told that the IBM 709 used inductive (rather than capacitive) storage for the main registers.

Fewer transistors, hence less die space. Same reason DRAM is more dense (hence larger) than SRAM. On 2016-May-28, at 7:12 PM, drlegendre . wrote:

<cctalk at classiccmp.org> the others storage Many early computers used "Dynamic" store for their registers. Certainly the Manchester Baby and Mk1 computers used Williams Tubes which need continual refresh. Not sure about the IBM 701 which used also used Williams Tubes for Main Store. Many early computers used either Williams Tubes or Delay Line type store, even for main registers. Pegasus was built like this.... Dave