Richard wrote: Ahh, integer only - I'm not too worried about FP operations. True. I think the 486DX (minus the 2) had the FP ops built in (did the 386DX??) If I remember right a few manufacturers made math chips for the x86 line. I always forget how darn *old* the humble 68k is :-) cheers Jules

You forgot one. Northstar* S100 system had an optional FPB it did BCD math (ADD, SUB, MUL, DIV) for two operand of 2 to 14 BCD digits. It was much faster than could be done with software in the Z80. EAE was PDP-8 The PDP11 series had multiple implementations including the FPP (2901 based) and the FIS for the 11/23cpu (F11). The 11/44 had a FPU that used a carload of 2901s. There were many other I'm sure I'm passing over. Allison On 03/07/2011 05:20 PM, Tony Duell wrote:

I 'forgot' many more than one, I can assure you. Thre was that AM9511 chip that was interefaced to many machines (I have seen an Apple ][ card with it on). I am not sure that counts, though. It didn't really extend the normal processor instrcuton set, rather it was a periphral for doing arithmetic. Maybe I've mis-remeebred the name. There was a hex-height Unibus board (jsut one obard) that was a hardware integer multiplier and divider. It was used with PDP11s that didn't ahve EIS (11/04, 1/05, etc) and it required special software support. It didn't add to the processor instruciton set, rahter you wrote the operands to particular I/O addreses and read the results back in the same way. I am pretty sure RT11 Fortran could use it. -tony

Does the Cray=1's Floating Reciprocal Approximation instruction count as a divide? --Chuck

In article <4D74F972.18273.17219F8 at cclist.sydex.com>, "Chuck Guzis" <cclist at sydex.com> writes: TRW and Weitek both made hardware multiplier chips for digital signal processing applications. Exactly when the chips were introduced, I don't know, but they were certainly present in the mid 80s. The IBM 701 had hardware multiply. I'm not sure about divide. This was 1953. -- "The Direct3D Graphics Pipeline" -- DirectX 9 draft available for download <http://legalizeadulthood.wordpress.com/the-direct3d-graphics-pipeline/> Legalize Adulthood! <http://legalizeadulthood.wordpress.com>

In article <4D7571AA.7090106 at gmail.com>, Jules Richardson <jules.richardson99 at gmail.com> writes: I can check my 6809 reference when I get home. -- "The Direct3D Graphics Pipeline" -- DirectX 9 draft available for download <http://legalizeadulthood.wordpress.com/the-direct3d-graphics-pipeline/> Legalize Adulthood! <http://legalizeadulthood.wordpress.com>

On 7 Mar 2011 at 18:00, Jules Richardson wrote: To the contrary, on the big iron, floating-point is central to the CPU design. Multiplies were usually pipelined (and sometimes duplexed) and took only a couple of cycles max. If you needed an integer multiply, you did it with the FP unit and recovered the unnormalized lower part of the double-precison product. The Cray reciprocal approximation (also found on the Intel 860) is used not because it's faster, than a real divide instruction, but mostly because the divide sequence can be broken down into a series of short instructions which then can be interleaved with the other work the processor is doing. An instruction that has a long execution time, can hold up issue of other unrelated instructions. The CDC 6600, if I recall correctly, did its divide by forming a table of trial divisors 3 quotient bits at a time. --Chuck

Tony Duell wrote: Yes, anything that includes a dedicated multiply or divide instruction as part of the instruction set; I suspect a lot of the early implementations fall into the "simple shift-add" that I mentioned due to the lack/cost of silicon. cheers Jules

Richard wrote: Hmm, good point. I had it set to 78 (TB's default), now changed to 75 though :) I'll have to have a look online and see if I can find any details. I see that Booth's algorithm was 1951 - much earlier than I expected and a year before the 701. I'm not sure when Wallace trees showed up... cheers Jules

Hi The Nicolet 1080 that was designed in 1969-1970 did 20X20 mulitply with 40 bit result. It also did divide of a 40 bit by a 20 bit to get 20 bit and remainder. It did these as steps from a multiply or divide single instruction. Each step was 1 usec, taking 20 usec to complete each operation. This takes one complete board full of DTL and TTL. As an additional function, it did bit reversal for addressing while doing FFT's ( Its main claim to fame ). Dwight

Hi The NC4000 had multiply/divide/squareroot steps The divide was non-restoring and required one extra step to get the last bit right. The NC4000 had an efficient step repeat instruction that made these operation only two instructions( except the divide restore was 3 if needed ). These were integer instructions. The NC4000 came out about the same time as the 386 as I recall and was a uProcessor. It was programmed in Forth as its native instructions and was often used as an excelerator board in PCs. Later it was bought by Rockwell and sold as the RTX2000. These were used in many space applications because it was static CMOS and could be easily rad hardened. Dwight

Looking through the Osborne book (Introduction to Microcomputers - Some Real Products / 1976), here's another to add to the list: the MicroNova/9440 microprocessor ca 1977 had built-in 16-bit multiply and divide instructions. Can anyone comment on how much use or production the MicroNova or Fairchild 9440 chips actually saw?

On 2011 Mar 8, at 12:14 PM, Chuck Guzis wrote: Sorry, going back to your earlier message I see that. I think I skimmed over it first time and thought of the mini rather than the microproc. You say the 9440 doesn't have M/D, the book does explicitly indicate they are present for the 9440 .. the book is in error?

On 2011 Mar 8, at 4:14 PM, Chuck Guzis wrote: I wonder if you have a later printing of Volume II than I have here. I do see near the beginning it states the 9440 implements only 'the LCD of Nova features', but on page 17-20 in the instruction table there are X's for the M/D instructions in the 9440 column. On page 17-15 it says X in the column indicates the instruction is present. The stack operations listed next have no X, indicating they are missing on the 9440.

On 2011 Mar 8, at 5:00 PM, Chuck Guzis wrote: Interesting, Copyright 1976 edition here, no other printing dates. There is no page 17-44 in this edition. I guess somebody observed an error in this edition and corrected it, or perhaps Fairchild's preliminary design hope didn't make it to production. A little arcania..

Chuck Guzis wrote: Not true, at least going by my conversations with distributors at the time. They were sold through normal commercial distribution, to anyone willing to purchase the minimum order quantity, which was around 30 parts if memory serves. Since they were rather expensive parts, that didn't include me. Since the 9450 implemented the MIL-STD-1750A architecture, obviously the main customers were defense contractors and their subcontractors, but a friend who worked for a commercial avionics company said that they used it in some non-defense products as well. That suggests that the 9450 pricing was sufficiently reasonable that if you had a 1750A codebase that you wanted to use in a commercial product, it was viable to use the 9450. The Fairchild Nova-compatible parts might have seen more non-military use than the 9450, but I don't have even anecdotal evidence of that. Like the Fairchild parts, the SBP9900 was sold through distribution. It appeared in TI's OEM price list, though I don't recall the price.

Chuck Guzis wrote: No, but then there weren't many hobbyist boxes using the PPS-8, F100-L, PACE, IMP-16, WD16/MCP1600, LP8000, or iAPX-432 either. The conclusion I reach is simply that obscure microprocessors that had a relatively poor price/performance ratio saw little hobbyist use. The IM6100 wasn't nearly as expensive as the 9440, and there was more public-domain PDP-8 software than public-domain Nova software. Eric

Chuck Guzis wrote: People talk about "the entire chipset", but there wasn't such a thing. That would be similar to talking about a microcoded bitslice system using "the entire 2900 chipset"; the concept is meaningless. A 432 system had varying numbers of chips of varying types. The General Data Process was composed of two chips, so those were always used together, but aside from that constraint the number of chips of each type used in a system varied all over the place. A minimal system would need one GDP (43201 and 43202), and one IP (43203). The total cost for one piece each of the 5 MHz speed grade of those three chips in 1984 was $259. There were a few commercial customers, but I have no idea what they used it in. I don't think many of the PACE systems used National's special interface chips. It's not clear that those chips even went into production. Not even. Anyhow, that proves my point. Hobbyists weren't interested in things that had a poor price/performance ratio, and Just because hobbyists didn't use things doesn't mean that they were only available to the military.

What do you mean by 'instruction set'. In particular, what do you do about machines (PERQ, for example) that load their microocde at power-on and thus don't have a fixed machine code instrcution set. -tony

Now that makes the classic PERQ an interesting case. AFAIK all the standard microcodes for the classic PERQ had multiply and divide instruciton. The hardware did not, a PERQ 1 had nothing special, the 1A and later had the mulstep/divstep logic I mentioned in an earlier messsage. So at the microcode level you didn't a full multiply or divide instruction, althought you may have had something that helped. Both machine code and microcode were available to programmers, but the odd thing is that (at least under POS) you were not expected to write machine code (that's what th Pascal compiler was for ;-)), but you were expected to write microcode. The microcode machine (==hardware) is much better documented than the 'Q machine' that the standard microcode gave you at the machine code level. So does that have multiply and divide or not :-) The standard microcode fo the PERQ doe give ou multiply and divide, but it;'s arguable whether these are hardare instructions or not., There were parallel multiplier chips in the TTL family. Some of them were clearly programmed PROMs. Good luck in fidning them (I have a few, which I am hanging on to...) You might want to take a look at how the PERQ did it. The extra logic on the 1A CPU for mulstep/divstep is not complicated (one extra shift register, and some control logic). And it's docuemtned. -tony

Christian Corti wrote: Maybe that depends on the complexity of the microcode sequencer and whether the microcode itself is able to do loops and branches? All the outside world sees is a hardware interface, though, so either way I'd still class it as hardware from that point of view. As I mentioned to Tony though, I'm really interested in CPUs that supported multiply/divide "out of the box" - needing to change the microcode or add a math copro don't count, even if once added they were transparent to the programmer. cheers Jules

Hi If anyone comes across a Diehl Combiton or a SCM marchant Cogito and doesn't want it laying around, I'd love to have one. I fiddle with on when I was working for the University of Miami. I used it to run data from paleotemperature stuff and C14 dating stuff. I never had any external storage. I can recall if it was tape of punch cards. It was all hand wired transistors as I recall. All packet into the box. It had two delay lines, one for data and the other for program. I recall cleaning the photo cell that was used on powerup. It had a two hole metal tape. One the clock and the other the data. I never did figure out how it coordinated the delay line with the tape. The tape didn't seem to have any speed control. Dwight Dwight

On Wed, 9 Mar 2011, Rick Bensene wrote: I am just in the process of analyzing a Combitron. With the help from Klemens, who read out the steel tape with his LAB8/e, I was able to disassemble the firmware of the machine. The CPU itself is hardwired and has 32 opcodes (5 bits called syllable). Eleven syllables make up a word. The contents of the steel tape is nothing but the program that implements the calculator. Here is an example, it's the contents of (R delay line) word 95 that implements the idle loop (waiting for a key press). The three-digit numbers are octal, the left one is a P word syllable, the right on a P_ (= not P) one. The P_ word of the I phase represents the opcodes. Word 95 (P / P_): 000 023 c 97 clear I_P 000 005 - 99 substract word 1 000 024 C 2 negative -> jump to 4 000 001 T1 6 test keyboard line 1 000 010 T2 8 test keyboard line 2 000 024 C 10 key pressed -> jump to word 12 000 030 W1 14 wait 000 000 (cnt) 16 000 031 W0 47 wait 000 013 (cnt) 49 000 025 F 93 jump to word 95 (loop) Yes, and that makes the machine *very* interesting. It is even more minimalistic than the LGP-30. True, and according to the service manual there existed test tapes to check out the machine with the help of an oscilloscope. I've counted the number of FFs: twelve for data processing and nine for clock and timing signals. The twelve FFs are the VZ register (i.e. V, W, X, Y and Z) that hold an opcode during execution; M, R and Q in line with the delay lines; A, B, C used for miscellaneous purposes during arithmetic operations; and E indicating a double or long order. All documents for the Diehl that I could get my hand on are on our FTP server (ftp.informatik.uni-stuttgart.de/pub/cm/diehl). Page 182 of the PDF document Diehl.pdf lists the opcodes of the machine, they are basically the same as those printed in Frankel's patent (also on the server). The difference between Frankel's and Diehl's design is mainly the increased word length of 55 instead of 40 bits. Christian

The 6809 was not microcoded. -- Ian