22 Nov
2006
22 Nov
'06
12:53 p.m.
Back in the early 70s, I did a computer science degree and was
taught that a simulator was a program and an emulator was a
microprogram, both to execute the instruction set of another
computer, but at a different level.
There is another class of simulation I have been considering
lately. For machines like my ICT 1301, which I would guess
has about ten thousand gates, it would be possible to write a
program which does a gate level simulation on a fast machine
like my 2GHz Mac. You could even simulate the signals in
the machine, hook up a simulated oscilloscope and look at
the waveforms. The slow rise times and overshooting might
not be possible to show of course, but maybe even this could
be added. You could even simulate logic faults for educational
purposes and show how they used to be tracked down via the
console, the logic diagrams and an oscilloscope. Now that
really would be a historical/educational tool. Or am I just dreaming?
Could I OCR the old line printer listings of the interconnection lists
and use them to build the simulator?
Simulating the audio output (which is pulsed on most conditional
branch instructions) is another issue I am thinking about. Modern
computers can obviously make the sounds, but how do I convert
from a live stream of speaker reversals into what a
modern
machine needs?
Roger.
22 Nov
22 Nov
8:57 a.m.
Roger Holmes wrote:
There is another class of simulation I have been
considering
lately. For machines like my ICT 1301, which I would guess
has about ten thousand gates, it would be possible to write a
program which does a gate level simulation on a fast machine
like my 2GHz Mac. You could even simulate the signals in
the machine, hook up a simulated oscilloscope and look at
the waveforms. The slow rise times and overshooting might
not be possible to show of course, but maybe even this could
be added. You could even simulate logic faults for educational
purposes and show how they used to be tracked down via the
console, the logic diagrams and an oscilloscope. Now that
really would be a historical/educational tool. Or am I just dreaming?
Certainly I don't see why you couldn't implement this at the gate level; I
suppose it's just a massive data structure of signal lines and logic
functions. Maybe for it to work accurately you have to simulate the
propagation delays of the various logic gates - but assuming it's all straight
digital logic I would have thought it would work.
Could I OCR the old line printer listings of the
interconnection lists
and use them to build the simulator?
Gah. Possibly, depending on quality. At least something that old should be in
a pretty regular typeface, so if the OCR procedures get any of it right then
they stand a good chance of doing the whole lot. It'll still be a pain to
proof-read though!
Simulating the audio output (which is pulsed on most
conditional
branch instructions) is another issue I am thinking about. Modern
computers can obviously make the sounds, but how do I convert
from a live stream of speaker reversals into what a modern
machine needs?
Well I suppose on a lot of Unix systems it's just a case of opening /dev/audio
and spitting data down the line - maybe the mac's no different?
cheers
Jules
1:04 p.m.
In article <3D76FD40-1741-45F2-96BE-CA6EF1FCEFBC at microspot.co.uk>,
Roger Holmes <roger.holmes at microspot.co.uk> writes:
There is another class of simulation I have been
considering
lately. For machines like my ICT 1301, which I would guess
has about ten thousand gates, it would be possible to write a
program which does a gate level simulation on a fast machine
like my 2GHz Mac. You could even simulate the signals in
the machine, hook up a simulated oscilloscope and look at
the waveforms. The slow rise times and overshooting might
not be possible to show of course, but maybe even this could
be added. You could even simulate logic faults for educational
purposes and show how they used to be tracked down via the
console, the logic diagrams and an oscilloscope. Now that
really would be a historical/educational tool. Or am I just dreaming?
Such things exist already to simulate chip designs. There are a
number of gate-level simulators out there, probably even some free
ones by now. When you write verilog/VHDL design code, this gets
compiled into gates. You might do gate-level simulation on the design
at that point and look at I/O signals and so-on. IIRC, gates are
compiled into instances of "standard cell libraries" for ASIC designs
and then manufactured. (The standard cell implements a very small
scale logic component and specifies all the transistor layout for
implementing the logic.) For an FPGA, your gate-level design is
compiled into an FPGA configuration and is very similar to "standard
cells" except that each and every cell is identical in size and number
of I/Os, whereas in an ASIC the standard cells will be different
sizes depending on the complexity of the logic and amount of I/O.
Could I OCR the old line printer listings of the
interconnection lists
and use them to build the simulator?
You could use them to capture the design and then simulate the design,
yes.
Simulating the audio output (which is pulsed on most
conditional
branch instructions) is another issue I am thinking about. Modern
computers can obviously make the sounds, but how do I convert
from a live stream of speaker reversals into what a modern
machine needs?
You have to simulate the analog effects of the pulsed output to
generate a waveform.
--
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23 Nov
23 Nov
3:57 a.m.
Roger Holmes wrote:
...
There is another class of simulation I have been
considering
lately.
...
it would be possible to write a
program which does a gate level simulation on a fast machine
like my 2GHz Mac.
I'm not trying to be a pain, but I'd call that verilog (or vhdl),
for which many fine compiler/interpreters exist.
You could even simulate the signals in
the machine, hook up a simulated oscilloscope and look at
the waveforms.
they do that as well. overshoot/undershoot requires something like
spice, however, which can be done but is more work because you need more
detailed/accurate models.
Could I OCR the old line printer listings of the
interconnection lists
and use them to build the simulator?
yes. I did that with the CADR. I cheated a little since I was able
to find the original CAD files and used those to extract a net list,
but all I had was a net list.
It's not hard to turn a net list into verilog which will simulate.
(well, for the purposes of this discussion. there are issues. let's be
kind however, and assume a synchronous design.)
Simulating the audio output (which is pulsed on most
conditional
branch instructions) is another issue I am thinking about. Modern
computers can obviously make the sounds, but how do I convert
from a live stream of speaker reversals into what a modern
machine needs?
as long as you don't need "real time", you can get the output into
a file and play it off-line.
-brad
6604
days inactive
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participants (4)
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brad＠heeltoe.com -
julesrichardsonuk＠yahoo.co.uk -
legalize＠xmission.com -
roger.holmes＠microspot.co.uk