Thanks.? Feeling good today after a bit of frustration with development not going faster. Our plan is to produce a Unibus board as well, we just chose the QBUS first.? A Unibus version of the hardware ought to be a fairly straightforward adaptation of the QBUS board while the QBUS modules in Verilog will just have to be replaced with Unibus versions.? The busses work pretty similarly so we're expecting that to also be relatively straightforward.? Yeah, I've told myself that before.? :-) For the Unibus (actually, this should work with Q18 QBUS systems as well), we plan to also implement the Able ENABLE+ functionality which would give 11/70 size memory.? We'll have some SDRAM onboard that we'll use for RAM disks but we'll carve out 4MB of that for machine memory and include mapping tables to access it.? This will, of course, require you to modify your OS to support this non-standard memory.? Noel has already done so for v6 Unix.