6 Dec
2016
6 Dec
'16
7:51 a.m.
From: Glen Slick
You should also hang out at vcfed forum in addition to
hanging out here.
I barely have time to keep up with the things I'm already into (actually,
strike that - I _don't_ have time to keep up already :-)! So I'm going to
have to pass.
Interesting about the FP11 stuff, though. I wonder, however, if those 11/20
mentions are more aspirational, rather than something that was actually done,
and later dropped? I say this knowing a modest amount about how the KA11 CPU
in the 11/20 works, and a bit about how the FP11-B interfaces to the host CPU.
For one thing, it would take some modifications to the KA11 to recognize
floating point instructions, so that it can wake up the FP11-B to handle
them. But that turns out to be the easy part; it would take further mods to
the KA11 because the FP11-B expects the host CPU to do data fetches, etc on
its behalf. (See Figure 2-3 in the FP11-B MainManual.) This latter function
can't be off-loaded onto a separate interface unit, as it needs access to
register contents held in the CPU.
I don't have the time to look into this further, but if someone is interested
they'd need to study the FP11<->CPU interface, and in particular look at how
the KB11 supports memory operations requested by the FP11-B - I wouldn't be
suprised if there's some microcode in the KB11 to support those memory
operations.
Noel
6 Dec
6 Dec
11:56 a.m.
On Dec 6, 2016, at 7:51 AM, Noel Chiappa <jnc at
mercury.lcs.mit.edu> wrote:
[data fetch] can't be off-loaded onto a separate interface unit, as it needs access
to
register contents held in the CPU.
Yeah, it?s pretty interesting! My guess would be that it was a separate register/command
oriented interface, sitting on the Unibus, and didn?t actually interface directly with the
11/20 CPU? Such an interface could limit the instructions ?fed? to the FPU to those
accessing its internal registers, etc. But who knows? :-)
I?ve gotten quite deep into the design of the FP11-B and associated KB11-A interfacing
during my debug (which is how I noticed all the 11/20 refs in the docs, circuitry, and
microcode), but I?m pretty ignorant of the 11/20 having never worked on one.
I wouldn't be surprised if there's some
microcode in the KB11 to support those memory operations.
Yes, there certainly is ? quite a bit of it actually. The are F/CLASS branches off all
three of the A, B, and C forks.
?FritzM.
1:13 p.m.
On Dec 6, 2016, at 2:56 PM, Fritz Mueller <fritzm
at fritzm.org> wrote:
I don't know anything of a DEC product along those lines, but a college classmate of
mine (Bill Black, Lawrence Univ. class of 1975) built a floating point coprocessor for our
PDP11/20 that was a Unibus peripheral. I helped with the software interface. The device
had 4 registers, two for source and two for second source and result. They appeared at
several different bus addresses; you'd select the operation to perform based on which
address you used. The device would start when the 4 source words had been loaded, then a
read cycle of the result register would simply be held off until the operation was done
(since it would complete well within the SSYNC timeout).
The implementation took, if I remember right, one hex-sized wire wrap board.
paul
On Dec 6, 2016, at 7:51 AM, Noel Chiappa <jnc
at mercury.lcs.mit.edu> wrote:
[data fetch] can't be off-loaded onto a separate interface unit, as it needs access
to
register contents held in the CPU.
Yeah, it?s pretty interesting! My guess would be that it was a separate register/command
oriented interface, sitting on the Unibus, and didn?t actually interface directly with the
11/20 CPU? Such an interface could limit the instructions ?fed? to the FPU to those
accessing its internal registers, etc. But who knows? :-)
2720
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fritzm＠fritzm.org -
jnc＠mercury.lcs.mit.edu -
paulkoning＠comcast.net