On 01/14/2017 08:18 PM, dwight wrote: And maybe waiting for a interrupt? That's what I di when I'm building simple 8085 that interrupt driven. Let it loop doing repetitive stuff if anything, an example is the old days refreshing Dram. Then use RSTx.5 to force it into a active do something mode and when done back to the loop. A current project for myself has the 8085 runnign a simple multitasking OS and the loop runs through the task table and every task retruns to the loop. Interrupts are real time events or priority events that need out of sequence attention. The 8085 makes that fairly simple. I'd bet the Executel is doing that, refershing display and scanning for events with some interrupt driven for out of sequence response. Correct. IO/m will only stay high for an IO cycle for all memory cycles it goes low (instruction fetch, execute plus memory read or writes ). IO/m (there is a bar over the m) also goes high during a RST 5.5, 6.5, 7.5 and Trap if interrupts are enabled along with INTR. It could be you have a chip with a blown input (stuck low).. However doing that test is rather inconclusive as there is so much other state activity to track. Note during IO the a0-7 is mirrored to A8-15. Hummm... 4116 dram, that means you have external refresh logic or they are going cheap and doing refersh on a interrupt (or maybe) timed loop. A real schematic is likely a great aid too. Allison

On Sun, Jan 15, 2017 at 1:02 PM, Adrian Graham <witchy at binarydinosaurs.co.uk> wrote: But do you know it''s not doing I/O. OK IO/M is never going into the right state for I/O, but what that _really_ means is that the 8085 is never executing any IN or OUT type instructions. But of course memory mapped I/O is possible (storing or loading at particular locations that happen to be I/O devices) on any processor that can access memory (including the 8085). I've seen small 8085 and Z80 control systems with only memory-mapped I/O. I don't think I've seen any daft questions yet! Why do you assume it's a keyboard controller? It might be, but it could be other things; THe 8741 is the EPROM version of the 8041. It's a 8048-like microcontroller with a couple of latches on-chip so it can be used as a peripheral from another processor (here the 8085). You need to trace the I/O lines from the 8741 to see if they go to the keyboard. Are these potted blocks, or can you see the components on them? Could this be part of the serial data transfer? There will be incoming data at 1200 baud. There should be some kind of demodulator (maybe one of the modules) and a serial-to-parallel converter You've not mentioned a serial chip (is there one), if not then I would expect it to be simulated in software. Maybe on the 8085, maybe on the 8741. The last basically says that either the 8741 has data to send to the 8085 (OBF = Output Buffer Full) or is ready for data from the 8085 (IBF = Input Buffer Full) I would be surprised if a 'closed' system like this did anything so complicated. More likely to be doing things like shifting characters around and then responding to an interrupt for keypress or incoming character. -tony

On Tue, Jan 17, 2017 at 1:15 AM, Adrian Graham <witchy at binarydinosaurs.co.uk> wrote: Basically, memory mapped I/O means having devices addressed as memory that perform I/O functions. You access them with the same load/store instructions that you use on real memory. On some processors (6502, 6800, 68000. PDP11, etc) that's all you have, there are no special I/O instructions. On others (8080, 8085, Z80, PDP8, P850, etc) you have special I/O instructions accessing I/O devices. The address spaces are totally separate, I/O location 0 has nothing to do with memory location 0. On the 8085, an I/O instructon (IN or OUT) will cause IO/M to be asserted (other state from when the CPU is accessing memory). Note that on a machine with I/O instructions (like the 8085) there is (a) nothing to stop you having memory mapped I/O (that processor can access memory), and (b) nothing to stop you having a mix of memory mapped and I/O mapped I/O. You might have simple devices mapped as I/O ports, but video memory (which is a sort-of I/O device in that storing something there causes it to appear on the screen) memory-mapped. As an aside, the TRS-80 model 1 had almost everything (video, keyboard, printer port, etc) _memory mapped_, the only standard I/O mapped device was the cassette unit. Ah.... I can see what appear to be thick-film resistors on them (the black rectangles). Are there more conventional components on the underside? Ah, I'd forgotten there was an SAA5070 on this board... What is the tape drive? That board has a distinct look of Philips about it. What tapes does it use? If I were a gambling man I would guess at Phlips minicassettes (not microcassettes). I think I know that drive... If it is the drive I am thinking of, I have one somewhere, meaning I can look up the capacitors. But I would expect the thing to produce video without it. I don't suppose you have a logic analyser? This is the sort of problem that would have me using said instrument to see what the processor is executing. -tony

On Tue, Jan 17, 2017 at 7:15 PM, Adrian Graham <witchy at binarydinosaurs.co.uk> wrote: It's very likely to be I/O mapped as it's only a couple of locations. [...] Do be careful, the substrate is a brittle ceramic material... That's the one. It's a Philips mechanism. I have at least one somewhere. I will try to find it. I don't think I have the schematic for it, but at least I can look at the PCB and find component values. Yes. It sounds like the processor is not initialising the video system, clearing video RAM, etc. Now either the processor is waiting for an interrupt (but from what)? or ir's not running the right code. CPU trouble, ROM troublem, RAM trouble, address decoder trouble? Can you clock the analyser from an external input rather than sampling every 10us or whatever? If so, clock it from the Rd/ signal and grab the 16 address lines (8 on the processor pins, 8 on an address latch, most likely a 74LS373, which you will have to find!). Now you can see the sequence of locations that the CPU is reading. Most (but not all) will be instructions. Find one, compare with the listing, see if the sequence makes sense. -tony

On 18 January 2017 at 20:13, Tony Duell <ard.p850ug1 at gmail.com> wrote: Thanks Tony :) -- adrian/witchy Owner of Binary Dinosaurs, the UK's biggest home computer collection? www.binarydinosaurs.co.uk

On 19/01/2017 15:47, "Tony Duell" <ard.p850ug1 at gmail.com> wrote: Brilliant, thanks! Nice to see what a clean unit looks like too, mine looks like it's been in the wars. I'm back from a little break to see my Missus so I'll clean up the board and see how bad the damage/rot is. Cheers, -- Adrian/Witchy Binary Dinosaurs creator/curator Www.binarydinosaurs.co.uk - the UK's biggest private home computer collection?

Back to the Executel after a few days relaxing :) On 17/01/2017 20:59, "Tony Duell" <ard.p850ug1 at gmail.com> wrote: I don't think I'll touch them, they're obviously part of the phone subsystem and I doubt I'll ever plug it into a phone line - I have several One Per Desks for that sort of thing if needs be. I remember becoming aware recently that it USED to look like it was reading all four ROMs but now just pulses ROM1. I'm still chasing down one particular clock source because there's a flip-flop LS74 that isn't getting anything at all, it's fed from an LS21 and an LS139 decoder which in turn is fed by A4 and A5 on the address bus. Having the whole board drawn out with all its connections is one thing but I need to put it into a logical schematic order. I can trigger it on the RD signal yes. There's 2 LS373s which both had dead inputs so I replaced those and made sure the signals were correct at all outputs. I'll have to lose A15 to latch onto RD (only 16 channels) but I'll give it a go. Cheers! -- Adrian/Witchy Binary Dinosaurs creator/curator Www.binarydinosaurs.co.uk - the UK's biggest private home computer collection?

On 21/01/2017 17:30, "dwight" <dkelvey at hotmail.com> wrote: I agree, it's also been wet and I don't know if that was pre-failure or just an effect of long term storage. There are also some (I assume) voice components like a -24V regulator (MC79L24A) that aren't getting power, I've just looked at the transformer that feeds it and that doesn't appear to be working. I'll post a separate pic of that. The modem in this case is an SAA5070 "LUCY" chip which I guess I can't easily test or even source a known working spare if it turns out to be faulty :/ Cheers -- Adrian/Witchy Binary Dinosaurs creator/curator Www.binarydinosaurs.co.uk - the UK's biggest private home computer collection?

On 21/01/2017 21:39, "Tony Duell" <ard.p850ug1 at gmail.com> wrote: Hm, no, none of the Saleae ones do external clocking, but I can set up a parallel oversample and use either the rising or falling edge of RD as a base, I wonder if that'll work... -- Adrian/Witchy Binary Dinosaurs creator/curator Www.binarydinosaurs.co.uk - the UK's biggest private home computer collection?

On 01/15/2017 08:02 AM, Adrian Graham wrote: All my life with hardware and software or so it would seem. I was a microprocessor product engineer at one time so this chip is one I roll hardware and software off the top of may head still. 8741A is likely keyboard controller. FYI its the eprom version of 8041A (the a is important). That part is easy to dump the EPROM and analyse as its only 1K. You can use a 8048 disasembler on that, nearly the same part save for the slave IO structure and a few instructions. FYI if you read the manual on the 8085 those MAY be in use as interrupts. The RIM instruction can read several things one is the state of the SID pin, also the state of the RSTx.x pins and the interrupt mask plus the status of the global interrupt enable. So its possible to use those pins (4 of them) as inputs without interrupts on all or none as you can read their state. RST7.4 is also special as its edge triggered (and transition activates it and it sets a latch) so unlike the other the state of the pin can be a pulse rather than a LEVEL. So it seems there is a keyboard interrupt and video (scan line) interrupt plus the RTC (time keeping and ?). You also have phone line events in there. FYI the software structure is familiar and likely straight out of the book for the 8085. You are preserving cpu status (AC-PSW), BC, DE, HL pairs, then working on the interrupt event. Also there is no rule that says IO must be IO-mapped its not uncommon for 8085 users to memory map IO just like 6800 and 6502 users as it offers a wider set of instructions for reading/writing or bit manipulation. You would also see /INTA (interrupt acknowledge) trigger. Do find a copy (its definitely on line) of the 8085 users manual, september 1978 as that has the best explanations and interface notes along with a detailed explanation of the RIM/SIM addition plus the interrupt systems behaviour. As they say its the Rosetta stone for the part. It was popular due to the availability of a interrupt structure adequate for small controller like systems and very easy to use. One note on 8085s... they all (never found an exception) have the "illegal opcodes" and they are indeed useful but _most_ commercial systems didn't use them. The vendors all of them sorta came to the conclusion that its a must to copy other vendors parts with all warts and weirdness. It really sounds like the unit suffered a high voltage transient (lighting, ESD, power supply over voltage). Another oddity, I with very rare exception (ti part) have never seen a high incidence of dead CPU chips. When I have it was pretty clear any survivors on the board were going to be few. Best example was my NS* system back in 79 took a lightning hit (bolt to the house antenna into the power distribution). It took about 300 pieces of TTL across 12 boards to bring it back to life. The only MOS device (had a hole in it) was a 8251A USART to the H19 terminal (also toasted). Z80 was still good and still in that system working to this day (along with a 8085A subprocessor). Sockets on the other hand have caused me no small amount of bedevilment. If its not machined pin and old its likely trouble. Ok, blown.... that make what I said earlier of a ESD incident likely. Check the DRAM too. Anything is a great help with that stuff as likely there were tricks used. We try. I enjoy working with 8048(family), 8085 and z80 have built with them for decades and do both HW and SW. Its fun to apply modern software techniques to old hardware as often they do it well even if not lighting fast. Allison

On 01/16/2017 08:37 PM, Adrian Graham wrote: http://bitsavers.informatik.uni-stuttgart.de/pdf/intel/MCS80/MCS80_85_Users… That's the later 1983 version but its the book you want. Likely history but if the parts move and the head is ok then clean it really well replace the caps and try. I had bought the Netronics explorer 8085 just before that bolt. That gave me a S100 chassis that would run even bad cards (think SDK85 with S100 bus interface). That made it possible to go a card at a time for function and level of function. Figure maybe 250 more more hours to get it running again and almost a year chasing random failures that were overstress induced. I still use that machine after dumping the 8kx8 cards for a larger 64K static it has performed well. Around 1980 it went through a series of mods and adds to upgrade it to multiporcessor. The turned pin are heavy and will stand that.... the copper under them or leading to them may be gone FYI vinegar or lemon juice will neutralize it, the battery (likely nicd) is alkaline. Rinse with water and dry. You can always inject a really slow processor clock, isn't rated for it but it does run down to less than 1khz. You can then watch signal with a bunch of leds. Keep plugging. That's why I like them. I can actually get it all in my head where 30million transistors and 4 cores causes major brain tilt. Allison

On 1/17/17 11:38 AM, Adrian Graham wrote: snippage>>>>> Figured that may help. The important spaces are the tape head face and the backside where the leads are. As systems of the day went it was cheap as the base unit plus the upgrades like the s100 frame, backplane and all were fairly inexpensive. I had power supply, memory and many of the parts to populate it. THe basic main board was not that expensive ass it was mostly unpopulated... Adding Level A though E added stuff but their cost barely doubled it to maybe the 400$ level. At that point its S100 bus but NO S100 boards and 4K ram on the main board and 8K of eprom (with M$ rom basic), the 8755 with a 2K monitor/debugger, and uses bit bash serial IO (very minimal hardware). I caught a break as around theyn I was testing JAWS 64K S100 dram board for Netronics in as many s100 crates as I had access to in 1978-79 (quite a few) so I worked a deal. Paid less as I could get the boards and mechanical bits and populate the day as it worked in everything I'd tried 8080/8085 or z80 plus one 1802! For the longest time the config was 64kdram board (Jaws), VDM-1, MITS SIOB, and NS* MDS floppy controller and it ran NS*dos or CP/M as needed. Without S100 boards in it it had monitor and 4K ram plus basic so that was enough to exercise ram cards, Io boards and the MDS controller. I later rewrote the monitor and pulled the MDS controller, VDM-1, and MITS SIO, to a Compupro interfacer II, so now it has an early IDE disk project for disk (a paltry 100mb drive). I still have it and use it. That's the rest of the story. Yes, but do the pins connect to other ICs now? I've see that stuff remove copper and leave pads. I must have a dozen or more with leads. handy for its here but not there... why? Allison

On 17/01/2017 18:22, "allison" <ajp166 at verizon.net> wrote: As luck would have it there's one on ebay right now, but it's a bit steep at $75 + nearly as much again in shipping. Also while it would be nice to have a fully functioning unit at the end of this I'm not sure the cassette is worth spending much time on apart from to replace what's obviously damaged and at least go for something that's seen by the controller. Only $400-ish? I'm surprised given the functionality it had. Heh, we all remember when 100mb was a luxury :) Yep, I've buzzed out all the lines between ROM chips as well as the RAM refresh, that was the second thing I did after cleaning up the battery residue and making sure I'd not had full-on socket rot like I had in my Amiga2000. Indeed. New ones are surprisingly expensive though, I paid ukp20 for a 14 pin one but it's paid for itself in not having to move 14 analyser cables -- Adrian/Witchy Binary Dinosaurs creator/curator Www.binarydinosaurs.co.uk - the UK's biggest private home computer collection?

On 01/15/2017 09:37 AM, Glen Slick wrote: I've seen that technique used to address a device, such as off-chip EEPROM--basically, rather than employ a separate latch for the address or map the device into memory space, a block of I/O addresses are used to directly access the device. It seems wasteful--and, as the code points out, rather inflexible, as the 8085 only has the immediate-operand IN and OUT instructions, but hey, it saves a couple of chips. So, the first thing that I'd look for is what devices on the board can be accessed in this fashion. --Chuck