24 Oct
2018
24 Oct
'18
9:01 a.m.
From: Paul Koning
A lot more comes from the CPU architecture. The
instruction set, of
course (arguably the first RISC).
An observation about RISC: I've opined before that the CISC->RISC transition
was driven, in part, by the changing balance of CPU speed versus memory
speed: with slow memory and fast CPUs, it makes sense to get as much
execution bang out of every fetch buck (so complex instructions); but when
memory bandwidth goes up, one needs a fast CPU to use it all (so simple
instructions).
It occurs to be that the same balance probably applies to memory _size_. When
memories are small, one wants dense code (which probably means CISC); only
with larger memories does RISC, with its less-dense code, make sense.
Noel
24 Oct
24 Oct
9:14 a.m.
On Oct 24, 2018, at 9:01 AM, Noel Chiappa via cctalk
<cctalk at classiccmp.org> wrote:
That sounds reasonable. But what does that say about the CDC 6000 series? It's RISC,
essentially, running on expensive and fairly slow memory. (Fast bandwidth due to 32 way
interleave, but roughly 8 cycles access latency.) I think the magic is that the
instruction encoding is very efficient, so you get the execution benefits of RISC without
the space penalties.
paul
From: Paul Koning
A lot more comes from the CPU architecture. The
instruction set, of
course (arguably the first RISC).
An observation about RISC: I've opined before that the CISC->RISC transition
was driven, in part, by the changing balance of CPU speed versus memory
speed: with slow memory and fast CPUs, it makes sense to get as much
execution bang out of every fetch buck (so complex instructions); but when
memory bandwidth goes up, one needs a fast CPU to use it all (so simple
instructions).
It occurs to be that the same balance probably applies to memory _size_. When
memories are small, one wants dense code (which probably means CISC); only
with larger memories does RISC, with its less-dense code, make sense. 
11:47 a.m.
On 10/24/2018 07:01 AM, Noel Chiappa via cctalk wrote:
An observation about RISC: I've opined before that
the CISC->RISC
transition was driven, in part, by the changing balance of CPU speed
versus memory speed: with slow memory and fast CPUs, it makes sense to get
as much execution bang out of every fetch buck (so complex instructions);
but when memory bandwidth goes up, one needs a fast CPU to use it all
(so simple instructions).
Maybe I need to finish my coffee before posting, but here goes anyway....
I thought memory and CPU speed used to be somewhat comparable
historically. And that such is NOT the case now.
As such, I feel like the industry has probably ended up going the wrong
way based on Noel's statement.
Am I failing to take into account the memory fetch buck being transacted
out of L1 / L2 cache (hopefully not main memory)?
Will someone show me a clue-by-four (but not hit me in the face with
it)? Please and thank you.
--
Grant. . . .
unix || die
1:53 p.m.
On 10/24/2018 9:47 AM, Grant Taylor via cctalk wrote:
On 10/24/2018 07:01 AM, Noel Chiappa via cctalk
wrote:
Statements made here may or may not reflect having morning coffee.
Back then it was throwing floating point numbers around, now it is
pixels at high speed. Regardless of the data, most of the time
(assuming simple hardware) you spend more time calculating the
effective address of data getting the data itself.
A RISC machine may have better space to cache stuff,but inside
knowledge how memory gets to the alu units from main memory was
visible until just a few years ago.
we have the NEW intel 800086 20% faster on benchmarks,using
C+++ MOO-GNU compiler. (Fine print older may have a 200% loss
of speed in some applications, re-compile with the latest (never
released to the public software) written in Chinese.*
I have no idea what is in a modern home computer, but I suspect
it still follows the same design of the IBM PC. Single CPU
with segmented memory and bit of DMA here and there.
Computer Science models are from the transistor era of computing
but don't reflect the internal speeds in the cpu chips.
To me they reflect the vacuum tube model of computing. Time to re-think
again.
Ben.
* if it was real fine print, I need a lawyer to read it.
An observation about RISC: I've opined before
that the CISC->RISC
transition was driven, in part, by the changing balance of CPU speed
versus memory speed: with slow memory and fast CPUs, it makes sense to
get as much execution bang out of every fetch buck (so complex
instructions); but when memory bandwidth goes up, one needs a fast CPU
to use it all (so simple instructions).
Maybe I need to finish my coffee before posting, but here goes anyway....
I thought memory and CPU speed used to be somewhat comparable
historically.? And that such is NOT the case now.
2:22 p.m.
On 10/24/2018 11:57 AM, Al Kossow via cctalk wrote:
On 10/24/18 10:53 AM, ben via cctalk wrote:
Am I really, every thing is so backwards compatable with the classic
PC's I don't see much new other than what was hacked on.
I am dealing with archiecture model here, the real hardware don't matter
anyway. If it takes X cycles to read memory, it still X cycles where
memory can be 10uS or 10pS. Ben.
I have no idea what is in a modern home computer,
but I suspect
it still follows the same design of the IBM PC. Single CPU
with segmented memory and bit of DMA here and there.
Wow...
You are out of touch, aren't you.
2:31 p.m.
On Oct 24, 2018, at 2:22 PM, ben via cctalk <cctalk
at classiccmp.org> wrote:
On 10/24/2018 11:57 AM, Al Kossow via cctalk wrote:
Single CPU, segmented memory? No. Multiple CPUs (8 or so in my laptop, many more in
servers). Flat 64 bit address space.
It's true that the original 8086 instruction set lives on with all its warts, and many
more added over the years. And yes, I guess that you *can* run them in 32 bit segmented
mode if you're crazy. But that's not how they are actually used. The same
applies to other successful architectures: MIPS, IBM 360. Or programming languages --
consider C for a particularly horrid example, or worse yet C++.
Al is right. You might benefit from some more studying of these subjects.
paul
On 10/24/18 10:53 AM, ben via cctalk wrote:
Am I really, every thing is so backwards compatable with the classic
PC's I don't see much new other than what was hacked on. I have no idea what is in a modern home computer,
but I suspect
it still follows the same design of the IBM PC. Single CPU
with segmented memory and bit of DMA here and there.
Wow...
You are out of touch, aren't you.
4:17 p.m.
New subject: modern stuff
On 10/24/2018 12:31 PM, Paul Koning wrote:
Well I can still run DOS BOX and get my nice 8086 instruction set.
On Oct 24, 2018, at 2:22 PM, ben via cctalk
<cctalk at classiccmp.org> wrote:
On 10/24/2018 11:57 AM, Al Kossow via cctalk wrote:
Single CPU, segmented memory? No. Multiple CPUs (8 or so in my laptop, many more in
servers). Flat 64 bit address space.
On 10/24/18 10:53 AM, ben via cctalk wrote:
Am I really, every thing is so backwards compatable with the classic
PC's I don't see much new other than what was hacked on. I have no idea what is in a modern home computer,
but I suspect
it still follows the same design of the IBM PC. Single CPU
with segmented memory and bit of DMA here and there.
Wow...
You are out of touch, aren't you. It's true that the original 8086 instruction set
lives on with all its warts, and many more added over the years. And yes, I guess that
you *can* run them in 32 bit segmented mode if you're crazy. But that's not how
they are actually used. The same applies to other successful architectures: MIPS, IBM
360. Or programming languages -- consider C for a particularly horrid example, or worse
yet C++.
All the computer science books push RISC now. EVEN KUTH has gone to the
DARK SIDE.
The point I was making and it got lost, for efficient programing the
programmer has to know some times the fine detail of cpu and memory.
With the way hardware keeps being revised often for more profit, nobody
knows the hardware any more.
Al is right. You might benefit from some more
studying of these subjects.
That may be true, but I can't change the market place for crappy
designs, since for
now I am locked into a windows OS. I use a free FPGA and PAL programing
software.
paul
70's computers are more interesting. That is why do we have PI computers
running PDP 8 emulators?
Ben,
5:37 p.m.
New subject: modern stuff
On Oct 24, 2018, at 4:17 PM, ben via cctalk <cctalk
at classiccmp.org> wrote:
It's all in what you want to do. If your interest is mostly the software, as it is
for many of us, then running emulators makes a lot of sense. If your interest is the
machine architecture, you might want to reverse engineer the design and implement it in an
FPGA. Depending on how deep you want to go, that might be a functional model or a gate
level model. A functional model may not tell you a whole lot more than a software
emulator does; a gate level model is often hard to pull off but if you can do it, it will
tell you everything you want to know about the original design including all its
undocumented strange properties.
And if you enjoy working on old electronics, there's no substitute for the original
iron. That's not an option if none exists any longer, or so few that people don't
dare powering them on. For example, it would be neat to run an EL-X8, but that's not
going to happen, there's only one left. At least it is preserved in a real museum.
As for myself, I've done all of the above: work on SIMH and DtCyber, work on a gate
level model of the CDC 6600, and (occasionally) run my old Pro-380.
paul
...
70's computers are more interesting. That is why do we have PI computers running PDP
8 emulators? 
5:58 p.m.
New subject: modern stuff
On Wed, Oct 24, 2018 at 2:18 PM ben via cctalk <cctalk at classiccmp.org>
wrote:
Well I can still run DOS BOX and get my nice 8086
instruction set.
I've heard many different adjectives used with regard to the 8086
instruction set, but this is the first time I've heard it described as
"nice".
Admittedly there are worse ones.
7:45 p.m.
New subject: modern stuff
On 10/24/2018 3:58 PM, Eric Smith wrote:
On Wed, Oct 24, 2018 at 2:18 PM ben via cctalk
<cctalk at classiccmp.org
<mailto:cctalk at classiccmp.org>> wrote:
Well I can still run DOS BOX and get my nice 8086 instruction set.
I've heard many different adjectives used with regard to the 8086
instruction set, but this is the first time I've heard it described as
"nice".
Admittedly there are worse ones.
What about Intel's forgotten object oriented kitchen sink processor.
IAPX-432 better or worse?
Ben.
7:58 p.m.
New subject: modern stuff
On Oct 24, 2018, at 7:45 PM, ben via cctalk <cctalk
at classiccmp.org> wrote:
On 10/24/2018 3:58 PM, Eric Smith wrote:
Was that the one designed around Ada?
I remember looking at that way back when the paper "Tablet, the computer of the year
2000" was published -- thinking it might be a suitable engine for that. I also
throught APL might be good because it's terse. Oops. Totally missed the fact that
most computer users are application users, not programmers.
paul
On Wed, Oct 24, 2018 at 2:18 PM ben via cctalk
<cctalk at classiccmp.org <mailto:cctalk at classiccmp.org>> wrote:
Well I can still run DOS BOX and get my nice 8086 instruction set.
I've heard many different adjectives used with regard to the 8086 instruction set,
but this is the first time I've heard it described as "nice".
Admittedly there are worse ones.
What about Intel's forgotten object oriented kitchen sink processor.
IAPX-432 better or worse?
Ben.
8:36 p.m.
New subject: modern stuff
On Wed, Oct 24, 2018, 17:58 Paul Koning via cctalk <cctalk at classiccmp.org>
wrote:
No, but it's the one that Intel's marketing department said was designed
for Ada.
What about
Intel's forgotten object oriented kitchen sink processor.
IAPX-432 better or worse?
Ben.
Was that the one designed around Ada?
8:35 p.m.
New subject: modern stuff
On Wed, Oct 24, 2018, 17:45 ben via cctalk <cctalk at classiccmp.org> wrote:
On 10/24/2018 3:58 PM, Eric Smith wrote:
I wouldn't call it a "kitchen sink processor"; some of it's problems
are
actually with things that are missing. However, it's a VCISC, and the
instruction set isn't really comparable to anything else.
If I had to design a computer for either general-purpose or embedded use,
I'd definitely choose 8086 over iAPX 432, but that isn't because I consider
the 8086 instruction set to be particularly good.
On Wed, Oct 24, 2018 at 2:18 PM ben via cctalk
<cctalk at classiccmp.org
<mailto:cctalk at classiccmp.org>> wrote:
Well I can still run DOS BOX and get my nice 8086 instruction set.
I've heard many different adjectives used with regard to the 8086
instruction set, but this is the first time I've heard it described as
"nice".
Admittedly there are worse ones.
What about Intel's forgotten object oriented kitchen sink processor.
IAPX-432 better or worse?
25 Oct
25 Oct
2:06 p.m.
New subject: modern stuff
One of my postgraduate school CS professors worked on the iAPX 432 and his
tidbit about the history of its development was that, whenever the EEs were
confronted with a hardware-level problem by the CSs, the EEs would
universally respond with, "Oh, well, that can be fixed by you software guys
with a SMOP (small matter of programming).", in the microcode, and Intel's
reference assembler, linker, and compilers.
Obviously, he returned to academia before the project collapsed in a heap,
and he might have had to scramble and compete with other departing CS PhDs
(who would also have hung around too long). Many would probably be looking
at another job where microprocessor microcode, assembler, linker, compiler,
and system-level library development experience would have been highly
desirable, and perhaps where the EEs were more reasonable. Plus, he didn't
have to put "Served on what became the sunken shipwreck iAPX 432" on his
resume/CV. That's because it wasn't yet at the Sixth Phase in the Six
Phases of a Project, "Punishment of the Innocent, and Rewards for the
Non-Participants".
On Wed, Oct 24, 2018 at 6:35 PM Eric Smith via cctalk <cctalk at classiccmp.org>
wrote:
On Wed, Oct 24, 2018, 17:45 ben via cctalk <cctalk
at classiccmp.org> wrote:
On 10/24/2018 3:58 PM, Eric Smith wrote:
I wouldn't call it a "kitchen sink processor"; some of it's problems
are
actually with things that are missing. However, it's a VCISC, and the
instruction set isn't really comparable to anything else.
If I had to design a computer for either general-purpose or embedded use,
I'd definitely choose 8086 over iAPX 432, but that isn't because I consider
the 8086 instruction set to be particularly good.
On Wed, Oct 24, 2018 at 2:18 PM ben via cctalk
<cctalk at classiccmp.org
<mailto:cctalk at classiccmp.org>> wrote:
Well I can still run DOS BOX and get my nice 8086 instruction set.
I've heard many different adjectives used with regard to the 8086
instruction set, but this is the first time I've heard it described as
"nice".
Admittedly there are worse ones.
What about Intel's forgotten object oriented kitchen sink processor.
IAPX-432 better or worse?
2:23 p.m.
New subject: modern stuff
Jim Manley wrote about a professor's experience in the iAPX432 team.
Didn't at least part of the team continue the project as the BiiN /
960MX?
-- Jecel
2:37 p.m.
New subject: modern stuff
On 10/25/18 11:23 AM, Jecel Assumpcao Jr. via cctalk wrote:
Didn't at least part of the team continue the
project as the BiiN /
960MX?
Yes.
Eric Smith can explain the whole history if he chooses to.
Here is what he has on line for the 432
http://www.brouhaha.com/~eric/retrocomputing/intel/iapx432/
10:17 p.m.
New subject: modern stuff
Tangent:
I have a large bin of perhaps a hundred working (last checked circa 2002)
single board computers in the warehouse (Western Pennsylvania) with i960
cpus if anyone's interested.
They were the Switch Control Processors from FORE Systems ASX200
switches, quite fully functional little computers and all self-sufficient
on one board. When we ported to x86, the poor i960 ones became unwanted
extremely rapidly; hence the surplus. Never had the heart to remand them
to the skip.
There's Serial, Ethernet, 7 segment display array, flash, RAM, clock,
etc. and a VME bus interface. Guys used to hook them naked to a couple
wires for power source and run them in their office window to scroll
messages. Would make for a swell massively, if lethargically, parallel
compute project.
Would enthusiastically trade for pdp11 stuff, or donate to interesting
project even if you have nothing to offer.
thx
jake
On Thu, Oct 25, 2018 at 6:16 PM Al Kossow via cctalk <cctalk at classiccmp.org>
wrote:
On 10/25/18 11:23 AM, Jecel Assumpcao Jr. via cctalk wrote:
Didn't at least part of the team continue the
project as the BiiN /
960MX?
Yes.
Eric Smith can explain the whole history if he chooses to.
Here is what he has on line for the 432
http://www.brouhaha.com/~eric/retrocomputing/intel/iapx432/
2:48 p.m.
New subject: modern stuff
On 10/25/18 11:06 AM, Jim Manley via cctalk wrote:
Obviously, he returned to academia before the project
collapsed in a heap,
and he might have had to scramble and compete with other departing CS PhDs
(who would also have hung around too long). Many would probably be looking
at another job where microprocessor microcode, assembler, linker, compiler,
and system-level library development experience would have been highly
desirable, and perhaps where the EEs were more reasonable. Plus, he didn't
have to put "Served on what became the sunken shipwreck iAPX 432" on his
resume/CV. That's because it wasn't yet at the Sixth Phase in the Six
Phases of a Project, "Punishment of the Innocent, and Rewards for the
Non-Participants".
Sigh, I remember the 432 being talked up by "Fast Eddie" our Intel
inside sales guy. "Micro mainframe" will be the best thing since the
bread knife.
We began to get an inkling of trouble when we requested ballpark
estimates of the cost of the various chips (the 432 is not a single chip
microcomputer--the basic family, as I recall was no less than three
(43201, 43202 and 43203) QIP chips. The cost for the set given to us in
the range of 4 figures.
As time went on, Eddie talked less and less about this and then went
completely silent--his response was basically "you don't want to know".
I don't recall if this was before or after performance benchmark numbers
started to appear.
While this was a failure on a spectacular level, it was by no means the
only misstep by Intel. The i860 RISC CPU at one time was even being
endorsed by BillG as a possible personal computer basis. I think that
the follow-on, the i960 was somewhat successful.
One thing you need in this business is a good back-of-the-neck sense.
Sometime in the late 1970s, I was invited up to Beaverton by Tek to
interview for the position of project manager for their new color
graphics display terminal. I don't recall many technical details--it
was a one-day visit. Tek was enthusiastic about getting me on board and
had even scheduled the movers. About 4 days before they were set to
arrive, I called off the offer--I'd had a really terrible dream about
the project and couldn't shake the cold sweats.
It turned out that the project came in late and way above estimates for
Tek, with layoffs resulting. A bullet dodged by a dream.
--Chuck
5:32 p.m.
New subject: modern stuff
On Thu, Oct 25, 2018 at 12:48 PM Chuck Guzis via cctalk <
cctalk at classiccmp.org> wrote:
endorsed by BillG as a possible personal
computer basis. I think that
> the follow-on, the i960 was somewhat successful.
Note that the i960 was totally unrelated to the i860. The i960 is actually
a follow-on to the iAPX 432.
The 432 led to the BiiN joint venture with Siemens. The BiiN processor was
a RISC but with 33-bit memory words containing a tag bit to distinguish
data from capabilities, to allow the 432-style object architecture with a
RISC base.
BiiN was unsuccessful, so Intel disabled the tag bit of the processor and
called it the i960. A later version of the i960 had the tag bit enabled.
(the 432 is not a single chip
microcomputer--the basic family, as I recall was no less than three
(43201, 43202 and 43203) QIP chips.
The General Data Processor (GDP) was split between two chips, the 43201 and
43202. It is the real "processor" of the 432 system.
The Interface Processor (IP), is a single chip, the 43203. It is used with
a conventional microprocessor, typically an 8086, known as the Attached
Processor (AP),
An iAPX 432 system could potentially contain up to 255 processors in total,
with an arbitrary mix of GDPs and IPs. You need at least one GDP. A system
to run the iMAX 432 operating system generally needed two IPs.
The cost for the set given to us in
the range of 4 figures.
The chips weren't actually that expensive; they were roughly $150 each for
the 7 MHz speed grade. The board- and system-level products were quite
expensive.
The i860 RISC CPU at one time was even being
26 Oct
26 Oct
8:55 a.m.
New subject: modern stuff
On 2018-10-25 14:48, Chuck Guzis via cctalk wrote:
While this was a failure on a spectacular level, it
was by no means the
only misstep by Intel. The i860 RISC CPU at one time was even being
endorsed by BillG as a possible personal computer basis.
the i860 found at least a little niche on graphics boards, so somehow
not a complete failure ;-)
9:10 a.m.
New subject: modern stuff
On Fri, 26 Oct 2018, emanuel stiebler via cctalk wrote:
On 2018-10-25 14:48, Chuck Guzis via cctalk wrote:
I worked for a company that made supercomputer boards out of the i860 at
one point - at the time (very early 90's) they were blindingly fast,
40Mhz, 3 instructions per clock cycle which, since one was a floating
point multiply and add meant that it was pretty good - at the time.
However it was a royal PITA to code for although a 32-bit CPU, it would
read memory 64 bits at a time (actually 128 IIRC to satisfy the cache),
with half that 64-bit word being an instruction for the integer unit and
half for the floating point unit, so you effectively had to build a
floating point pipeline by hand coded instructions, so 8 (I think)
instructions to load the pipeline, then each subsequent instruction would
feed another value into the pipe, then another 8 at the end to empty it.
Great for big matrix operations, rubbish for a single add of 2 FP numbers.
The issue came when you wanted to take an interrupt - the overhead of
flushing the pipe, reloading it all for the next context, and so on really
bogged it down.
Not to mention writing assembly code in 2 columns...
There were quite a few systems built with about 30 boards in them, each
having 2 x i860's and a good few MB of RAM (64MB I think) built.
-Gordon
While this was a failure on a spectacular level,
it was by no means the
only misstep by Intel. The i860 RISC CPU at one time was even being
endorsed by BillG as a possible personal computer basis.
the i860 found at least a little niche on graphics boards, so somehow
not a complete failure ;-)
27 Oct
27 Oct
9:04 a.m.
New subject: i860, was : Re: modern stuff
On 2018-10-26 09:10, Gordon Henderson via cctalk wrote:
I worked for a company that made supercomputer boards
out of the i860 at
one point - at the time (very early 90's) they were blindingly fast,
40Mhz, 3 instructions per clock cycle which, since one was a floating
point multiply and add meant that it was pretty good - at the time.
However it was a royal PITA to code for although a 32-bit CPU, it would
read memory 64 bits at a time (actually 128 IIRC to satisfy the cache),
with half that 64-bit word being an instruction for the integer unit and
half for the floating point unit, so you effectively had to build a
floating point pipeline by hand coded instructions, so 8 (I think)
instructions to load the pipeline, then each subsequent instruction
would feed another value into the pipe, then another 8 at the end to
empty it. Great for big matrix operations, rubbish for a single add of 2
FP numbers.
The issue came when you wanted to take an interrupt - the overhead of
flushing the pipe, reloading it all for the next context, and so on
really bogged it down.
Not to mention writing assembly code in 2 columns...
There were quite a few systems built with about 30 boards in them, each
having 2 x i860's and a good few MB of RAM (64MB I think) built.
There was actually a nice PC Mainboard from Hauppauge, with an i486 &
i860 on the same board ...
Always wanted to have one of those, never found a used one. And it was
running some king of Unix back then ...
http://www.geekdot.com/hauppauge-4860/
Cheers
7:23 p.m.
New subject: i860, was : Re: modern stuff
CHM has a rather large Intel Paragon system.
I just recently snagged the software and manuals for it on eBay
which we didn't have
http://www.computerhistory.org/collections/catalog/X1644.99
and others
http://www.computerhistory.org/collections/search/?s=intel+paragon
29 Oct
29 Oct
9:39 p.m.
New subject: i860, was : Re: modern stuff
On 10/27/18 15:04, emanuel stiebler via cctalk wrote:
There was actually a nice PC Mainboard from Hauppauge,
with an i486 &
i860 on the same board ...
Always wanted to have one of those, never found a used one. And it was
running some king of Unix back then ...
http://www.geekdot.com/hauppauge-4860/
I have a computer with this mainboard.
I received a DOS version of the Portland Group's C compiler for i860
along with it. The DOS software also had a "run860"
program, to -- you guess it -- run programs on the i860.
I then wrote a Linux version of "run860" and created an assembler
toolchain for Linux to target i860 (using GNU binutils).
I was able to compile and run the "blink" demo from the manual on Linux
instead of DOS. And some other assembler
programs written by me.
These things can be found on ftp://ftp.groessler.org/pub/chris/i860 .
At this time I was in contact with the original author of the i860
binutils support, Jason Eckhardt. With his help and
patch to gcc, I was able to compile newlib with gcc for i860. But I've
never tested it beyond compilation.
Jason also told me that he had a modified Linux kernel for i860 (which
IIRC was for a then already old version of Linux).
Since according to the motherboard manual, interrupts from hardware
devices always interrupt the i486, and not the
i860, I never asked him for this version. Getting that to work, with
i486 and i860 cooperation, didn't appeal to me.
regards,
chris
27 Oct
27 Oct
2:02 p.m.
New subject: modern stuff
On 10/26/18 6:10 AM, Gordon Henderson via cctalk wrote:
However it was a royal PITA to code for although a
32-bit CPU, it would
read memory 64 bits at a time (actually 128 IIRC to satisfy the cache),
with half that 64-bit word being an instruction for the integer unit and
half for the floating point unit, so you effectively had to build a
floating point pipeline by hand coded instructions, so 8 (I think)
instructions to load the pipeline, then each subsequent instruction
would feed another value into the pipe, then another 8 at the end to
empty it. Great for big matrix operations, rubbish for a single add of 2
FP numbers.
My impression of the i860 was that it might have been fun for about 2
weeks for which to code assembly, but after that, you'd really start
looking hard for an HLL to do the dirty work for you. While there's a
sense of accomplishment over looking at a page of painfully
hand-optimized code that manages to keep everything busy with no
"bubbles", you begin to wonder if there isn't a better way to spend your
life.
--Chuck
26 Oct
26 Oct
4:26 p.m.
New subject: modern stuff - i860
Two design wins I remember:
TrueVision, the AT&T computer graphics people that did the TARGA video boards had
software to back the board sales up, a 3D animation package TOPAS.
Beautiful, but dog slow even on the fastest 25MHz PCs at the time, so they had ported it
to the i860 as an add in card. I think render frame rates went from minutes to a few
seconds. I used TOPAS under DOSBox on a current PC, and it screams. Its up on Vetusware
if your interested.
The famous graphic supercomputer hardware war, Ardent / Stellar, the later merge and
purchase by Kubota had two applications, Dore' and Advanced Visualization System,
AVS.
These impressive machines were canned, and Kubota came out with a i860 desktop for
graphics. I remember the introduction in Houston, and the 3D geophysicists and petro
exploration guys were all over it. the graphics demos and computation capability was
amazing.
I never knew what happened to that workstation.
________________________________
From: cctalk <cctalk-bounces at classiccmp.org> on behalf of emanuel stiebler via
cctalk <cctalk at classiccmp.org>
Sent: Friday, October 26, 2018 5:55 AM
To: Chuck Guzis; General Discussion: On-Topic and Off-Topic Posts
Subject: Re: modern stuff
On 2018-10-25 14:48, Chuck Guzis via cctalk wrote:
While this was a failure on a spectacular level, it
was by no means the
only misstep by Intel. The i860 RISC CPU at one time was even being
endorsed by BillG as a possible personal computer basis.
the i860 found at least a little niche on graphics boards, so somehow
not a complete failure ;-)
27 Oct
27 Oct
2:29 a.m.
New subject: modern stuff - i860
On 2018-10-26 16:26, Randy Dawson wrote:
Two design wins I remember:
TrueVision, the AT&T computer graphics people that did the TARGA video
boards had software to back the board sales up, a 3D animation package
TOPAS.
Beautiful, but dog slow even on the fastest 25MHz PCs at the time, so
they had ported it to the i860 as an add in card.? I think render frame
rates went from minutes to a few seconds.? I used TOPAS under DOSBox on
a current PC, and it screams.? Its up on Vetusware if your interested.
The famous graphic supercomputer hardware war, Ardent / Stellar, the
later merge and purchase by Kubota had two applications, Dore' and
Advanced Visualization System, AVS.
These impressive machines were canned, and Kubota came out with a i860
desktop for graphics.? I remember the introduction in Houston, and the
3D geophysicists and petro exploration guys were all over it.? the
graphics demos and computation capability was amazing.
Most high end graphics on DecStations had an i860 on it. Rumor is, they
were made by Kubota, but never saw a drawing or schematics to prove it ...
29 Oct
29 Oct
5:50 p.m.
New subject: modern stuff
On Fri, 26 Oct 2018 at 14:56, emanuel stiebler via cctalk
<cctalk at classiccmp.org> wrote:
the i860 found at least a little niche on graphics
boards, so somehow
not a complete failure ;-)
And of course it was the N-Ten CPU on the Microsoft Dazzle
motherboard. The main product developed on that mobo was codenamed
after the CPU -- "NT"...
https://www.itprotoday.com/windows-server/windows-server-2003-road-gold-par…
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24 Oct
24 Oct
7:02 p.m.
New subject: modern stuff
It was thus said that the Great ben via cctalk once stated:
On 10/24/2018 12:31 PM, Paul Koning wrote:
The first RISC chips appears in the 80s, making them over 30 years old
now. Even the MIPS and SPARC architecture (RISC based) are nearly (if not
already) 30 years old (I used systems with both in the early 90s).
If anything, the DARK SIDE won in that we seem to be perpetually stuck
with a glorified 8080 (that is so complex that it contains an additional,
embedded no-quite-so-glorified 8080 to help it boot up! [1]).
-spc (It kind of reminds of the MCP from TRON ... )
[1] https://en.wikipedia.org/wiki/Intel_Management_Engine#Disabling_the_ME
It's true that the original 8086 instruction
set lives on with all its
warts, and many more added over the years. And yes, I guess that you
*can* run them in 32 bit segmented mode if you're crazy. But that's not
how they are actually used. The same applies to other successful
architectures: MIPS, IBM 360. Or programming languages -- consider C for
a particularly horrid example, or worse yet C++.
All the computer science books push RISC now. EVEN KUTH has gone to the
DARK SIDE. 
2:34 p.m.
On Oct 24, 2018, at 11:22 AM, ben via cctalk
<cctalk at classiccmp.org> wrote:
On 10/24/2018 11:57 AM, Al Kossow via cctalk wrote:
Not so much anymore. ;-)
None of the current OS?s have anything to do with the segmentation of x86
as it?s all gone as part of the 64-bit ISA. It?s still there if you use the older
legacy modes but those are not used other than booting (and that will go
away soon too).
The lower level architecture is also significantly changed with out-of-order
execution, deep pipelines and large L1/L2/L3 caches. Even though from
an ISA perspective, the x86 has only a few visible integer registers, with
OOO and register renaming (I think the current CPUs have 192 registers
that they can use for ?renaming?) it isn?t much of an issue.
Oh, and I almost forgot. You always have multiple CPUs (typically 2-8 on most
mobile and desktops?and that?s without hyper-threading enabled).
Servers are typically 16+ per socket and there can be upto 8 sockets
per server without getting esoteric (so for a typical 4 socket server you
can get 64-128 CPUs).
TTFN - Guy
On 10/24/18 10:53 AM, ben via cctalk wrote:
Am I really, every thing is so backwards compatable with the classic
PC's I don't see much new other than what was hacked on.
I am dealing with archiecture model here, the real hardware don't matter
anyway. If it takes X cycles to read memory, it still X cycles where
memory can be 10uS or 10pS. Ben.
I have no idea what is in a modern home computer,
but I suspect
it still follows the same design of the IBM PC. Single CPU
with segmented memory and bit of DMA here and there.
Wow...
You are out of touch, aren't you.
2:56 p.m.
On 10/24/18 11:22 AM, ben via cctalk wrote:
Am I really, every thing is so backwards compatable
with the classic
PC's I don't see much new other than what was hacked on.
I am dealing with archiecture model here, the real hardware don't matter
anyway. If it takes X cycles to read memory, it still X cycles where
memory can be 10uS or 10pS. Ben.
Well yes and no--memory speeds haven't scaled to the same extent that
CPU speeds have. Consider that in 1982, you could get 80 nsec 4116s,
where your CPU was typically run between 4 and 8MHz.
CPU speeds have improved about a thousandfold, so that a 4GHz CPU isn't
particularly exotic, but I don't know of many 80 psec. consumer-grade
DRAMs.(it takes light about 80 psec to travel one inch).
--Chuck
3:21 p.m.
On Wed, 24 Oct 2018, Al Kossow via cctalk wrote:
On 10/24/18 10:53 AM, ben via cctalk wrote:
It's either that or BOFH-level trolling. :)
g.
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I have no idea what is in a modern home computer,
but I suspect
it still follows the same design of the IBM PC. Single CPU
with segmented memory and bit of DMA here and there.
Wow...
You are out of touch, aren't you.
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