Ok here's a quick rundown of the errata so far (there's probably a lot more I haven't noticed), some stuff might need to be done as images/drawings due to errors in some figures: page 4-19 subheading 4.4.4.1: Omission: PEEK(address) is perfectly valid code and isn't in the list of valid basic operators. (Tested on emulation and 10 print peek(0256) then run does print 194 (0xC2 appears at offset 0x100 in address space).) page 5-3 figure 5-2: Error/Omission: the "DIP SELECTION" box next to "SYSTAT A" should have a second arrow pointing to it from the address bus (since DIP selection is based on the low 3 bits of the address (offsets 0x40-0x47)) page 5-10: Error: the rom 3 extends from 6000-67ff, not 6000-63ff as listed. The chip contains 6000-6fff but the area between 6800 and 6fff is blank, 0x00s. page 5-14: Table 5-3 I/O Register Addresses: Error: the write register decode for address 0x47 does not have the read bit set to 1 (this is an obvious typo) Error: The KYBDW write register is listed as if it is at offset 0x78; it is actually at offset 0x68. Error/Omission: the read register for SYSTAT A is listed as 0x40; it is actually mirrored to 0x40-0x47 but the dipswitch bit read to d2 for each of those addresses is different. (the switches read for each of the addresses from 0x40 to 0x47 in d2 is, base-0, so switch 1 is 0, 2 is 1, etc: 1,3,5,7,6,4,2,0 ) page 5-15: Table 5-4 Program RAM addresses: Omission: the c000-ffff ram area is not populated on the vk100 board, though ram is refreshed as if it was there. (it may have been intended as an expansion kit by DEC but was never sold as far as I'm aware) Error: Table 5-5 I/O ROM Microcode Address: the address for the row read/column drive mapping of the keyboard ranges area every 16 bytes, and the firmware reads it at 7ff0-7fff) page 5-27: Figure 5-17: the "translator input" left side of this figure has some major row/column offset/duplication issues. The correct contents should be: 11 10 9 8 7 6 5 4 3 2 1 0 (000) TA200 1 0 0 0 0 0 0 0 0 0 (001) TA200 1 0 0 0 0 0 0 0 0 1 (002) TA200 1 0 0 0 0 0 0 0 1 0 (003) TA200 1 0 0 0 0 0 0 0 1 1 --------------------------- (004) TA201 1 0 0 0 0 0 0 1 0 0 (005) TA201 1 0 0 0 0 0 0 1 0 1 (006) TA201 1 0 0 0 0 0 0 1 1 0 (007) TA201 1 0 0 0 0 0 0 1 1 1 --------------------------- (010) TA202 1 0 0 0 0 0 1 0 0 0 (011) TA202 1 0 0 0 0 0 1 0 0 1 (012) TA202 1 0 0 0 0 0 1 0 1 0 (013) TA202 1 0 0 0 0 0 1 0 1 1 --------------------------- (014) TA203 1 0 0 0 0 0 1 1 0 0 (015) TA203 1 0 0 0 0 0 1 1 0 1 (016) TA203 1 0 0 0 0 0 1 1 1 0 (017) TA203 1 0 0 0 0 0 1 1 1 1 --------------------------- The right table in the figure is correct. Page 5-29, Table 5-7: Error: The equation for "Overlay" should be M=AT(P+N) instead of M=A+(P+N) Page 5-30, Figure 5-19: Error: The labels on the two lines coming from the "SOPS" block are transposed; The top one should be "WHAT COLOR IS THE SCREEN" and the bottom one regarding the bit 0 reverse video bit. Omission: the line which SHOULD be "what color is the screen" (the one going to input B on the MUX) should have a note on the line noting that it is 4 bits wide, not one bit as is implied by the figure. The "What color is the data" line should have such a marking as well. Page 5-32 Figure 5-21: Error: the clock source for the down counter is NOT the "CHAR CLK" as listed, but the "DOT CLK". (This had me confused for a good 15 minutes before I spotted the error) Page 5-35: Omission/Ambiguity: The description of the "Screen Options (SOPS)" register is missing the bit numbers for each part of the described functions, and there are FOUR functions, not three. This could be better written as: 1. Blink Control/Mask (bit 3) 2. Background Color + Blink (bits 7,6,5,4) 3. I/O port control (EIA, 20 mA, hardcopy and self-test) (bits 2,1) 4. Normal/Reverse Video (bit 0) Page 5-38, Figure 5-23 Arbitrary Waveform Timing: Error: The Vector rom addresses listed at the top have address 23 missing and 33 duplicated twice; the correct pattern from left to right should be: 34 23 22 21 20 25 24 33 32 31 30 35 34 23 22 21 20 25 24 33 32 31 30 35 Page 5-42, Figure 5-26: Error/Ambiguity: the lines from "SOPS" to "I/O PORT SELECTOR" are labeled SL1 and SL0; the actual bits in the SOPS register these represent are bits d2 and d1. Page 5-53, Figure 5-33 and Table 5-10: the same ambiguity with SOPS bit labels SL1 and SL0 appears here. Nowhere in the tech reference does it mention they are bits d2 and d1. Page 5-57 Figure 5-37: Omission: the line from "ADDRESS LATCH" to "DECODER" (which is labeled A6-A0) is missing its (70<subscript>16</subscript>) marking; on figure 5-36 on the previous page (page 5-56) the marking is present. Page 5-62: Omission/Ambiguity: the description of SYSTAT A does not note anywhere in the tech reference that the bits read appear in SYSTAT A bits 6,5,4,3 for bits 3,2,1,0 of the nybble the current X and Y registers point to in VRAM. One possible error (I need to test this more), which appears on two successive pages: Page 5-66 Figure 5-42: *POSSIBLE* (Needs verify with keyboard and meter) the pins for SHIFT and CAPS LOCK are reversed; capslock should be pin 35 and shift pin 33 Page 5-67 Figure 5-43: *POSSIBLE* the KBD-R latch implies that capslock is D6 and shift is D7, when in reality they are the other way round. Hope that helps, If I run into more I'll send to the list as well. -- Jonathan Gevaryahu jgevaryahu at gmail.com jgevaryahu at hotmail.com