Subject: Re: large data transfert (write) to SDRAM at fixed frequency
From: Pierre-Marie BOYER <pm.boyer at wanadoo.fr>
Date: Mon, 31 Jul 2006 14:45:27 +0200
To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at
Le Dimanche 30 Juillet 2006 18:19, jim stephens a ?crit?:
Pierre-Marie BOYER wrote:
The ADC send data to the SDRAM through the DMA at a fixed rate during
may be 1 or 2 second, and is this process
can be stopped/disturbed by the internal refresh process of SDRAM ?
If yes, is there a solution, to manage the two process ( fixed
acquisition and SDRAM refresh cycle) ?
Thank you very much.
If you are only collecting ADC data at that rate, can you use an I/O mapped
device instead of DMA, and just poll and read the data? Or are you saying
that the ADC data will start up and run at some rate approaching the memory
cycle time for 1 to 2 seconds?
No, ADC data run at a fixed frequency (30 MHz) during several seconds,
so data, from the ADC, must be writen to the sdram at rate one byte every 0,03 usec,
during several seconds.
( ADC hasn't buffer).
But what happend when the SDRAM enter in its refresh cycle, which occurs every 64ms ?
Maybe this will help... Refresh is the periodic reading of all rows of a Dram.
If you were to do a bulk write and the number of bytes written exceed the number
of rows in the DRAM then refresh or not you will have refreshed the ram.
Nominally refresh is handled in two ways bulk, doing all the rows in one long
pass every so many mS as required by the devices. The better and more common
technique is to interleave refresh in between accesses such that you will have
accomplished refresh of all rows in the required time.
My, $.02 is if your running an ADC at 30mhz and the system has SDRAM you still
only using a fraction of the bandwidth and refresh is not an issue. Since your
writing nearly (30mhz*2sec-60Mbytes) 60mbytes of data you will refresh the ram
nearly 31.25 times in two seconds, likely more than enough to satisfy refresh.