Are there any good *detailed* descriptions about how the 3 cycle data break works on say, a pdp-8/I with an rf08 or df32? I've read 3-4 simple descriptions, but I'd like something that relates - in detail - to the cpu instruction cycles/states (i.e. f0-3,d0-3,e0-3). I'm curious what the exact state machine looks like. I'm also curious if the data break cycles occur as additional cpu states or if they overlap cpu states in any way. I'm resisted diving into schematics mostly due to lazyness (and work), but that may be the next step. I guess I have no seen any good 8/i "principles of operations" either, outside what is said in "Computer Engineering". any pointers/comments appreciated. -brad