28 Feb
2018
28 Feb
'18
5:15 p.m.
Is there a document that describes the bank 7 memory page and what
addresses are reserved for what?? I think I've seen this before but
can't seem to put my hands on it.
Another question, bootstrap is reserved for 173000, how many words are
allowed there for this?? How do the more complicated bootstraps, e.g.
microPDP11-53, accommodate this limitation?
Doug
28 Feb
28 Feb
5:32 p.m.
The various handbooks are useful. Processor, peripherals, and architecture handbooks all
give parts of the picture.
paul
On Feb 28, 2018, at 8:15 PM, Douglas Taylor via cctalk
<cctalk at classiccmp.org> wrote:
Is there a document that describes the bank 7 memory page and what addresses are reserved
for what? I think I've seen this before but can't seem to put my hands on it.
Another question, bootstrap is reserved for 173000, how many words are allowed there for
this? How do the more complicated bootstraps, e.g. microPDP11-53, accommodate this
limitation?
Doug
1 Mar
1 Mar
3:12 a.m.
On 02/28/2018 08:15 PM, Douglas Taylor via cctalk wrote:
Is there a document that describes the bank 7 memory
page and what
addresses are reserved for what?? I think I've seen this before but
can't seem to put my hands on it.
Another question, bootstrap is reserved for 173000, how many words are
allowed there for this?? How do the more complicated bootstraps, e.g.
microPDP11-53, accommodate this limitation?
Doug
I strongly suggest RTFM the PDP-11 handbooks.
Till you do...
Page 7 is? the upper most memory area and is reserved as EPROM and IO
peripherals. On many of the
PDP-11s that page is signified by asserting BBS7 ( a partially decode
address) and the MMU also
understands that peripherals live in that physical space be it 16/18/22
bit memory map.
Boot and diagnostic roms are a special case as more often their size was
not limited to the area of bank 7
but the available devices of the day.? They do however map roms so that
they cannot overlap the IO
devices.
FYI the microPDP-11/53 is the 11/23+ cpu card so you can look that up.
Allison
6:04 a.m.
On Mar 1, 2018, at 6:12 AM, allison via cctalk
<cctalk at classiccmp.org> wrote:
... and the MMU also
understands that peripherals live in that physical space be it 16/18/22
bit memory map.
That's true when the MMU is disabled; if so it supplies 1 bits for the upper bits for
page 7, and zeroes for the other pages. But if the MMU is enabled, all mapping goes
through its mapping registers, and page 7 is no longer special. By software convention,
kernel data page 7 is configured to point to the I/O page, but that isn't required.
If you wanted to be be perverse you could map the I/O page via page 6 and confuse a whole
generation of programmers.
paul
4:39 p.m.
On Thu, Mar 1, 2018 at 9:04 AM, Paul Koning via cctalk
<cctalk at classiccmp.org> wrote:
That's true when the MMU is disabled; if so it
supplies 1 bits for the upper bits for page 7,
and zeroes for the other pages. But if the MMU is enabled, all mapping goes through its
mapping
registers, and page 7 is no longer special. By software convention, kernel data page 7
is
configured to point to the I/O page, but that isn't required. If you wanted to be be
perverse you
could map the I/O page via page 6 and confuse a whole generation of programmers.
So if the I/O page is completely (all processor modes) unmapped is
there any way to recover besides a power cycle? Does the RESET
instruction disable the MMU?
-chuck
2268
days inactive
2269
days old
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allisonportable＠gmail.com -
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