On 11/23/06, Gordon JC Pearce <gordon at gjcp.net> wrote: Hmm... I would have thought that it was a 2MHz part, but some googling does show the B variant clocked at 8MHz. If that's the case, I wonder if it's possible to overclock Henk's "Real Console". That it is. It's also known as a "PTM" - Programmable Timer Module. Some light digging around seems to show that it's a 2MHz part. lot as in parts? sure. At 2K per chip, not that much actual storage, though. I agree (as I observed earlier). Still... any hints as to where the connector pins go would be handy. I don't think CompuServe made 6809-based Qbus CPUs, so I'd think this is some sort of peripheral, but it's functionality is not obvious to me. So far, we know what CPU it has, it's local SRAM space (16K), and that it has a timer. It must be getting its code from the host since I can't spot any ROMs, but once that load happens, _then_ what does it do? -ethan

Pete wrote: I left most of the original message intact. Yes, you can run the Blinkenlight Core Board (and I/O board) with an 8 MHz Xtal. The 6809 (B version) will run at 2 MHz, due to the E and Q clock generation. The 6809 uses a 4 MHz Xtal and one instruction cycle is one microsec. The 68A09 runs with a 6 MHz Xtal and the cycle is 666 ns. The 68B09 uses an 8 MHz Xtal and the cycle is, you guessed, 500 ns. The CPU "speed" equal clock frequency divided by 4. I hope I have the nanosec numbers right. The pdp8/e simulation runs at best performance, with a 68B09 at 8 MHz. All parts of the Blinkenlight Board set can handle that frequency. Also, for my floppy disk interface, to read FAT-12 floppy (DD, not HD) you really need that speed, otherwise you can not keep up the data rate the FDC presents the data stream. See my project folder ... The PTM (6840) has three 16-bit timer/counters IIRC, but you can find that in any old Motorola handbook. In a different thread, now on CCtalk (FPGA) is an interesting discussion. Till now I haven't said much, as I am just starting. Like Vince, I bought an FPGA from Xess. Actually we bought 4 with 4 people ... I just haven't had the time to start with my Xess module! There is a core for that FPFA that simulates a 6809 at 50 MHz, effectively giving an 80 ns cycle time! That would make the pdp8/e simulation run at the speed of the pdp8/s. The ultimate will be of course, not to simulate the 6809 in the FPGA, which in software simulates the pdp8, but let the FPGA simulate the pdp8 right away. With the I/O latches connected to the FPGA you would have a nice hardware simulation of the 8/e ... Just my thoughts. - Henk. This message and attachment(s) are intended solely for the use of the addressee and may contain information that is privileged, confidential or otherwise exempt from disclosure under applicable law. If you are not the intended recipient or agent thereof responsible for delivering this message to the intended recipient, you are hereby notified that any dissemination, distribution, or copying of this communication is strictly prohibited. If you have received this communication in error, please notify the sender immediately by telephone and with a "reply" message. Thank you for your cooperation.