On Sat, Apr 13, 2013 at 4:27 PM, Cory Smelosky <b4 at gewt.net> wrote: Maybe around $100 is a reasonable price for a CMD CQD-200/TM or CQD-220/TM, or Dilog SQ706A. The Emulex UC07 or UC08 seem to go for more of a premium.

On Apr 13, 2013, at 7:41 PM, Glen Slick wrote: That seems like an optimistic price on eBay, especially for chassis. They go for a lot on eBay and cost a lot to ship because they're HEAVY. You're better off trying to find someone (perhaps from this list) that has one to spare/sell that is close enough you can drive to. But yes, sometimes you can get really lucky on eBay. Or, if you live in the right part of the country (in the USA, that would be generally the right parts of California or Massachusetts), Craigslist/dumpster diving. I had rather little luck in MD, WV or PA, but I found a guy an hour and a half away in NJ who was willing to part with a nice BA11-S for less than a fortune. - Dave

On 04/13/2013 07:41 PM, Glen Slick wrote: I'd buy every one I could get my hands on if they really sold for that price. ;) Subtract the SCSI host adapter and you might be moving toward the right ballpark but it would still be a heck of a deal. -Dave -- Dave McGuire, AK4HZ New Kensington, PA

On 14 Apr 2013, at 00:23, "Dave McGuire" <mcguire at neurotica.com> wrote: Exactly! You need the total immersion. ;) Personally, I want to go the extra mile and keep the decorations period-accurate, too. ;)

On Sun, Apr 14, 2013 at 10:32:00AM -0400, Toby Thain wrote: Nice -- I totally did have a pair of fuzzy dice hanging from the DZ11 dist panel on my 11/34a in the 1980s! I can see how multi-hour SYSGENs are a trip for people who have a choice, but they were no fun in the old days when we didn't (especially swapping packs multiple times, with a risk of expensive damage at every step -- and a floppy-only SYSGEN is not funny) so I'm extremely relieved that those days are over. But of course, I'm biased. And I certainly did get a big kick out of it when I first got E11's raw floppy driver working and was able to boot RT-11 from 8"-workalike 5.25" disks. I didn't realize that series of clicks and whirs had been so deeply imprinted on my brain! John Wilson D Bit

On Apr 14, 2013, at 12:26 PM, David Riley wrote: Sorry, that's Gerard Putter, not Gerd Knorr. I'm confusing my Germanic software developers. :-) - Dave

On Apr 14, 2013, at 7:22, "Jerome H. Fine" <jhfinedp3k at compsys.to> wrote: (h) is part of it, but for some of us, it's also the feeling of accomplishment for keeping a 30+-year-old computer alive. The way I explain it to family and friends who don't get why I like spending time in the basement with old, loud computers when I have perfectly fine ones upstairs is that it's like people who maintain classic cars. Old cars are slower, less reliable and guzzle more gas than even a cheap newer one, but for some reason it's socially acceptable for people to tinker with *those*. For some of us (like me) for whom these machines are actually OLDER than us, it's a way of understanding computing of the past in a way that an emulator just won't do. For example, I mentioned that on Simh on a somewhat older laptop ran an RSX11-M SYSGEN in about a minute and a half, while a real 11/23 took about three hours. That was quite the revelation for me, and it's not something I would have fundamentally understood without the real hardware. The "collecting" aspect of it is fun as well, though I imagine that novelty wears off when you have a full basement and difficulty lifting even a BA11 box. I'm not saying your points are invalid, because they're not. If I were trying to maintain a commercial PDP-11 installation that didn't have special hardware to consider, I might prefer an emulator because it'll be faster and possibly more reliable (though I'm going to count on my 11/23 outliving my next 3 x86 servers). It's a different set of considerations. - Dave

On 2013-04-14 13:22, Jerome H. Fine wrote: If you have to ask, you wouldn't understand ;-) Anyway, I play/work with emulators a lot, both pdp11 and VAX, and yes, for a lot of work they are nice. Just switching container files, doing backup on a network is nice. But, then there is this thing going to the "other" office, flipping the switch, see some flickering on the lights, and hear the fans starting up, drives spinning up. Then the real vt100/vt220/vt340 terminals, 9-track tapes, it simply feels right. Probably: Mona Lisa as .jpg, versus the real thing? ;-) Cheers

Then obviously, we agree! Before the emulators were available, real DEC CPUs and other hardware was vitally important. I even became somewhat capable in regard to figuring our problems and putting systems together. One time, I even managed to assemble from switches, diodes, LEDs and resistors (along with a bit of wire and solder, of course) a front panel that would support what a 6 button front panel on a BA23 box has to support two MFM hard drives, including LEDs to display the WRITE PROTECT status of any floppy media in the RX50 drives. So I am not completely immune to the "Light Side" of the hardware. Since I have been writing programs for computers since 1960 (started with an IBM 650 using SOAP assembler), I am VERY aware that hardware has advanced far more than software. In fact, during the early years before operating systems with files and disk drives became available, the ONLY thing was hardware and the minimum software was only there to guide the single batch job at a time through the queue. The biggest single change was around 1966 when it became possible to support a large number of terminals which were able to EDIT online files which were then submitted as batch jobs to be executed one at a time. This allowed the shift from punched cards to online files to become possible. The system I worked on in 1967 was a CDC 3500 with a file structure that supported up to 6000 files residing on washing machine sized disk drives. But by 1980, DEC had developed and improved their operating systems and that software has finally started to become just as important as the hardware. Many others, including IBM had also started along those lines. In particular, CDC had an operating system for the 64 bit CPU, the STAR-100, which used virtual memory based in the 256 TerraByte address space. However, RT-11 finally became my focus, for many reasons, around 1980 and I don't think there has been a year since then, perhaps not even a month, that I have not run programs under that operating system. When Ersatz-11 was first released around 1995, it was rather limited and I used both real DEC CPUs and Ersatz-11 for a number of years. By 2002 when I upgraded to a 750 MHz Pentium III with 768 MB of memory and 40 GB hard drives, I started to used the PDP-11/83 less and less. What I still find so challenging is that even after 40 years, RT-11 still has a few bugs which crash the operating system and many bugs that need fixing. The basic structure of RT-11 is extremely solid and lends itself to many more enhancements that I ever would have believed. I have managed to enhance more than half of the SAV files and many of the device drivers along with the actual monitors, as well as writing new monitors such as SN(X).SYS, Symbolic Name List Pseudo Device Driver which does all of what PATH does for DOS. Recently, I have also enhanced the KED variants to support more than 24 lines and more than 132 columns. Jerome Fine

I don't have anything like a PDP-11. The oldest machine I have is probably a BBC Micro and the biggest, noisiest machine I have is an Alphaserver 2100. I've been known to mess about with trying (not very successfully) to get a sound card to produce a 400Hz background whirr that comes and goes as I move around the room. The sound of fans and disks does help create the right mood as long as it is not loud enough to be irritating. Not a problem in winter (except for the effect on system reliability). More of a difficulty in summer. Not necessarily. I've paid at most nominal amounts for most if not all of my older equipment although I have sometimes had to invest a little more for the parts and peripherals I occasionally need. I am not part of the crowd that collects old equipment hoping for it to increase in value. There would be an incremental cost to the world and the environment if I was to purchase hardware and software from companies producing the latest equipment and running the latest bugware. If it's fast enough, I am not bothered by how much faster it could be. Same. Same. I am fairly disorganised. Less disk space gives me an incentive to keep things tidy and get rid of clutter. I am slightly more worried about reliability of old disk hardware. However, I've managed to keep ahead of the disks that have died on me so far. I like the touch and feel of the original software as well as the hardware. If the hardware I want is not available and a good emulator is, I'll use the emulator to experience the software. I'll still use something pretty old to run the emulator on though. Regards, Peter Coghlan.

On 14/04/2013 19:47, Mouse wrote: Isn't that the fun of computing. There is a whole spectrum of what folks enjoy, and wouldn't the world be a boring place if it wasn't so. I am building an IBM1130 Emulation using an FPGA using Richard Stofers code., but I still run the IBM 1130 emulator.....

On 14/04/2013 20:17, Cory Smelosky wrote: Laurence Wilkinson has already done that for the 360/30. It will fit on the same board as the 1130. http://www.ljw.me.uk/ibm360/vhdl/ http://www.youtube.com/watch?v=walWU2MQ2OM He has posted on here and he is working on getting a real Selectric connected as the console. There are also implementions in FPGA of several other CPUs, including PDP/8 and PDP/11 (but not sure how complete the PDP/11 ones are). Some like Laurences are "gate acurate" emulations and others like Richards are "Behaviourial" so a kind of cross between software and hardware emulation. You can't really shrink the Selectric very much. It would be nice to do a 360/67 and run MTS though. My next project is going to be a Ferrantti Pegasus .. http://en.wikipedia.org/wiki/Ferranti_Pegasus but what I would really like for this are some of the GPO style switchs.... (They are GPO style because the British Post Office rang the telephone system in the UK for many years).... Dave G4UGM

On Sunday, April 14, 2013 21:04:38 Dave wrote: My fpga PDP11 is very complete. You can run all the historic operating systems on it, including 2.11BSD. And you can even hook it up to ethernet. No more need for a pc to simulate. Read about it at http://pdp2011.sytse.net/

On Sunday, April 14, 2013 21:21:18 Cory Smelosky wrote: Sure you could!

On 4/14/2013 2:55 PM, cclist at sytse.net wrote: Got one for sale? Ben.

On 14/04/2013 22:48, Sytse van Slooten wrote: I have the Nexys-2 which I got from Farnell, who I believe trade as Element14 in the US, but buying direct from Digilent looks OK. If you can find a tame student you may also be able to get one at an academic discount.

On 4/14/2013 3:48 PM, Sytse van Slooten wrote: Can you write up a complete shopping list needed for a PDP-11 system talked about on this list. Ben.

On Apr 14, 2013, at 19:19, Sytse van Slooten <cclist at sytse.net> wrote: I really like my two DE1s, though they're a little long in the tooth at this point. They're great to play with, lots of hobbyist-friendly interfaces (switches, buttons, 7-segment displays, VGA out and a serial port, plus the SD slot). No Ethernet, but they're also only $150 in the US. The DE2 has Ethernet and more goodies, but it's somewhat more expensive. I know Sytse has a load for the DE1, at least. - Dave

On 4/14/2013 5:19 PM, Sytse van Slooten wrote: I just ordered the de0 board from Terasic. What do recommend as good online reference for programing the FPGA? I still want to play around with some simple computers in the 18 to 24 bit width range and since I have to do it all from scratch, programing the FPGA for what bit length I like looks, to be easy. It will be interfacing the core logic to memory and I/O that I may need help with. Ben. PS. I used CUPL at one time for ALTERA CPLD's and I like using it.

On 4/24/2013 5:58 PM, David Riley wrote: They still I think have schematic entry. That serves me quite nicely for the work I want to do. Ben.

On Apr 24, 2013, at 10:27 PM, Jim Stephens <jws at jwsss.com> wrote: That's from Xilinx's new line that has a beefy ARM processor built into the chip which interfaces nicely to the FPGA logic. I don't know if you're likely to use that for a CPU project, though it's great for a lot of other things. The one that's on that board has approximately 3 times the FPGA logic that the DE0 has; if you really wanted to expand the FPGA logic for the same price, you could also try Terasic's DE2-115, which has more than twice the logic that Digilent board does (note that the Zedboard is only available to academic customers, and the DE0-115 has a lower price for academic customers). http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=502 I like Terasic's boards a LOT, and the DE2-115 comes packed with a lot of REALLY nice features for hobbyists (it's like the DE0 on steroids). The Xilinx toolchain which includes the Zynq devices is freely available as well. http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm Xilinx has a new toolchain out called "Vivado", but it's VERY new, and therefore somewhat unpolished. I haven't used it yet, but I hear unfavorable things from some colleagues. Stick with ISE for now. Like Altera, it runs on Linux and Windows just about equally well. The 360/30 project calls for an FPGA of about the size used on the DE0; the "1000K gates" Spartan 3 has about 17K logic elements, while the DE0 has about 16k. Manufacturers stopped using the "gate count" nomenclature a while ago because it's not particularly accurate or useful, so an LE count is usually better. That's also a really old board, and Xilinx has EOLed the original Spartan-3 line (the Spartan-3A and -3E lines are alive and well still). FWIW, a brief primer on FPGA nomenclature, if you're going to be looking at sizes: A "logic cell" or "logic element" usually means a 4-input, 1-bit lookup table with a (bypassable) 1-bit output register. This can implement any 4-input logic function (basically as a truth table) and optionally register it. The bigger FPGAs (Arria/Stratix for Altera, Kintex/Virtex for Xilinx) have bigger LUTs to implement more complex features in a single logic element, but their sizes are usually given in an "equivalent" 4-input LUT count; for example, an EP2S60 is a Stratix II (2S) with the equivalent of 60K LEs. It's kind of a hand-wavy number, because they essentially just apply a scalar multiple to the actual number of larger elements they have, but in the general case it's a lot more useful than the "equivalent gate count" numbers from a decade ago. In any case, you should be able to fit the 360/30 FPGA on the DE0, though you'll have to create the project file and do the pin assignments yourself. You'll also have to hack out any Xilinx-specific things in the VHDL if there are any, which is usually just PLLs and block RAMs in most smaller projects (there are other things that might be lurking, but they'd be unlikely in a project this size). I don't know about the /65, though; that's on a much bigger FPGA that has 110K equivalent LEs, and it uses PCI Express to communicate with the host PC to run as the channel. It doesn't have sizing info, but that project would definitely need significant mods to work with smaller boards. It might be a fun (if somewhat advanced) project to port it to work on the Zynq, since the built- in ARM would provide the functionality of the channel emulator quite nicely. No guarantees on whether the 360/65 part of it would fit in the FPGA, though, since there's no sizing info provided on the page (you could always try to download and build it, though the free software won't build for a Virtex5 that big; if you're really curious, I could build it with mine, since I have access to the full suite). - Dave

On Apr 25, 2013, at 10:50 AM, Camiel Vanderhoeven <iamcamiel at gmail.com> wrote: Didn't realize that was yours. Nice console! And nice project! I'll be interested to see what comes out of it and possibly contribute once my box of tuits is a little more full. - Dave

On Wednesday, April 24, 2013 19:58:37 David Riley wrote: I learned much about the way a cpu is implemented from the example in http://opencores.org/project,mcpu which is a minimally simple design, but it shows the basic concept very elegantly. The other thing that helped me a lot is that with the behavioral languages you should always have in the back of your mind some image of how it will translate to hardware - ie, not think like 'if this happens, then it will do that' but rather 'the if will cause a comparator to be made, which feeds an enable signal towards X'. Schematic capture can take you a long way, but it's much more 'hardware style' work than VHDL or Verilog. I initially thought I would like schematic capture a lot better, but after a couple of days of drawing, I changed my mind. The initial setup is fairly doable, but changing your design can be a headache with schematics. I think Altera's Quartus still lets you do schematics, but I'm not so sure about Xilinx' ISE.

On 04/25/2013 07:45 PM, ben wrote: Oh good lord, yes you have to register, get over it. It is VERY open. Opencores is a very well-respected organization. You type your name in order to gain access to gazillions of dollars' worth of IP. What the hell are people thinking these days?! -Dave -- Dave McGuire, AK4HZ New Kensington, PA

On 4/25/2013 6:06 PM, Dave McGuire wrote: Clearly the cost of tin foil is too low. Who says you even type your name. I can't recall the last time I did that at a site, and frankly don't care as long as the spam generated is traceable. If you own your own domain that problem is easily handled. I appreciate all the pointers and advise from those who have replied. My main target is the PDP 11, but hopefully will pick up some tools and learn something in the process. Jim

On 4/25/2013 9:18 PM, David Riley wrote: Good ... I'll send you the buggy logic after a few weeks. AHDL looks to be the cats meow for me, easy to program in like PAL's. I plan to use slow ripple carry to emulate TTL logic speeds -- 18 bits with a 1 MHZ memory cycle. DE0 looks to be a very nice board, ample memory for a small computer at a good price. I was planning to build something with 2901's but because the connectors I ordered did not work as well as I hoped this came along at the right time. I still plan to make a front panel for the DE0, to match the internal the CPU. I made a VGA controller for my Sounds like a C64 sprite controler would be easy, if you still can get a analog TV set up. Ben. PS. I do plan on finishing this project, I planned to finish it within the next 25 years. All my disposable income has gone into HI-FI equipment, the latest state of the art logic is not going away for a while.

On 25/04/13 11:53 PM, ben wrote: A whole C64 has been done. http://www.syntiac.com/fpga64.html http://www.youtube.com/watch?v=tGezOeGeNek --Toby

Well...can be. Personally, having to use an undocumented binary blob of a compiler - which, oh, by the way, almost certainly doesn't run on either the OS or the CPU architecture I want to run it on, even if I were willing to run it - kills the `fun' aspect dead. If you find it fun despite such things? More power to you. I'll stick to using my `fun' time for things that don't ick me out. Given the "use this closed proprietary compiler to generate an opaque blob which you throw at undocumented hardware" nature of FPGA dev, I'm not surprised. I suspect I'd be decent, possibly good, at FPGA programming. But until either someone is willing to pay me to find out or the hardware gets documented, that will remain unknown. I doubt I'm _entirely_ alone in that. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

On Apr 26, 2013, at 1:34 AM, alan at alanlee.org wrote: Mouse's objection is based on the fact that they don't document the functions of the configuration bitstream, without which you cannot write your own synthesis software. In the case of things like PALs and GALs, the datasheets for the device specify what each bit in the bitstream does as far as turning on minterms, inverting outputs, etc. The programming algorithms for GALs at least are proprietary (I think), but they have been reverse engineered fairly well. I don't really disagree; I think the bitstream functionality (note: this is distinct from the FORMAT of the bitstream, which Xilinx discloses without describing what the actual config bits do) should be open so that people can do more interesting things with the FPGAs. The fact that it is not does not stop me from using them, though, because I do not have as many serious reservations about using closed, proprietary software. The difference here is that CPU vendors don't have proprietary, hidden instruction sets (let's ignore undocumented diagnostic instructions for the moment). If you had a CPU that required you to use a proprietary compiler that generated code that you were contractually prohibited of one of the many others with an otherwise open architecture (I'm not talking about the masks, I'm talking about what you run on it). Sadly, there are no FPGAs that I am aware of that are open alternatives to the status quo. Mouse does not run Linux or Windows or x86 processors, to my knowledge. Xilinx and Altera both used to run on Solaris and HP-UX for Sparc and HP-PA, respectively, but those were discontinued many years ago. For modern FPGAs, you really need to be running pretty beefy, modern iron to compile in any sort of reasonable timeframe. My 8-core Xeon with 8 GB of RAM takes 45 minutes to compile even a medium-sized Arria II (Altera's mid-level FPGA) that's half-full, so I don't think a SparcStation 20 would be an ideal candidate for running the exhaustive search algorithms necessary for building modern devices, but if you were able to write your own generation software, you could at least route it yourself (with all the hazards that entails). - Dave

On Apr 26, 2013, at 12:45 PM, Mouse <mouse at Rodents-Montreal.ORG> wrote: My bad, I thought x86 was more or less banished from your domain. :-) Is the Super-H machine you're talking about a Dreamcast? Those are pretty neat machines, though I never had one myself. People are still releasing new (good) games for them, too! It's the complexity of the devices. It's not like CPU code, where everything is linearly executed; it's a lot closer to a PCB auto- router because it's a 2D search space of optimal routes. Except the problem is blown up to several hundreds of thousands of pre- routed nets to select from. The actual synthesis code (taking the HDL and turning it into a device-independent intermediate netlist) takes about as long as compiling the equivalent length of C code; it's the "fitting" process (taking the intermediate netlist, placing all the nodes, then choosing routes that will meet the timing constraints) that takes so long. Optimization on a C compiler usually involves some comparatively simple dataflow analysis and then eliminating redundancies which are revealed by said analysis. Fitting an FPGA involves making a best guess at what the optimum placement is (sometimes with "floorplan" guidance from the designer, which can help a lot) and then making many, many passes at what the optimum routes are to meet the timing constraints specified. I don't know what the exact algorithms are, since they're considered trade secrets, but I know the way at least Xilinx's software iterates looks close to a genetic algorithm (it keeps the most successful pass so far and varies it until it either closes timing or gives up). How long it takes obviously depends on the complexity of the design. If you just throw a 16-bit counter design in there, or a moderately complex design with a very slow clock, it's going to take a minute and a half to compile even on the biggest FPGA out there because it doesn't have to make many tries before it meets timing. But if you crank the clock in the timing model up to 1 GHz, it's going to try a whole lot more potential routes before it throws its hands up in disgust (within reason; if you did it with the 16-bit counter, it will very quickly converge on a "this is as fast as she goes, Cap'n" value anyway). Maybe. CAD algorithm design is a huge and active area of academic research, because there's a lot of money to be made if you can develop an algorithm that closes faster and gives higher maximum frequencies. I agree that it's incredibly dumb that the bitstream semantics are hidden. There's always an opportunity to reverse-engineer from subtly different builds, but I do think the EULAs probably prohibit that... if you did it for your own edification, though, no one would know. Alas. - Dave

On Fri, Apr 26, 2013 at 12:45:10PM -0400, Mouse wrote: I certainly get that. For me it's a matter of categories. I can't get the source code or schematics for my microwave oven, but while I'd certainly enjoy having them, it's fiiiine. It's just an appliance. It's irritating being denied full access to my own property, but I bought it to heat food, which it does. Same with my car's ECU, my musical tuner, digital watch, and don't get me started on the (*&^!@#*% TiVo which has had the wrong DST rules for several years now because I won't pay the protection fees for a piece of hardware I bought free and clear (for $400 for chrissake!). But at the same time, I've got a multi-lifetime backlog of stuff that IS open to hackery, and new interests cropping up all the time, and it's obvious I'll never get around to even 1% of it. So I gave up ages ago -- someone else can be in charge of web browsers and traffic lights and printers and PCB autorouters and all the infinite stuff that I wouldn't have the energy for even if well commented source code (plus build tools) were served up on a platter. Reinventing the wheels that DO interest me is already a full-time job. But I guess everyone draws the line in a different place... John Wilson D Bit

I don't know how true it is for you, but for me, (3) half the other clocks in the house _are_ computers, which _do_ get it right without manual intervention - and on which I can install new DST rules whenever I want. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

NTP is your friend. Turn on ntpdate at boot, and start ntpd with -g (or whatever the equivalents are for your OSes), and you should be fine. Or just tell all of them that the hardware clock is to be kept in UTC - of course, that assumes they're all non-broken enouigh to be capable of being told that.... /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

On 27/04/2013 08:51, Cory Smelosky wrote: These days I struggle to find something that needs a manual update. The clock in my TV , PVR and bedside radio (not a Tivo) all seem to update time so that works fine (and it syncs from DCF77 http://en.wikipedia.org/wiki/DCF77) so the clock must know how to remove the DST offset when its added. The Android Mobile which frequently gets used as a SatNav updates automatically as well.... I think I Central Heating still needs a manual update, as does by wrist watch , which I kind of wear as habit as I tend to check the time on the Android Phone. I guess I should include my Accutron Tuning Fork watches but the batteries in those only seem to last a couple of months so not a real issue....

On Apr 26, 2013, at 12:24 AM, Mouse wrote: Well, that's up to you. I understand your principles, and I'm certainly glad you stick with them even when it comes to personal inconvenience. They don't always line up 100% with mine, and I don't have much of a personal problem with running proprietary, closed software. Obviously, I'd PREFER it to be open, but for most cases, I'm not going to REQUIRE it. Those are my principles and not yours (not that I think you misunderstand, but I don't want anyone thinking that I think you're full of shit, because I don't). Me too. I don't use my "fun" time writing iPhone games anymore, partly for similar reasons. I suspect that has a lot less to do with the dearth of good FPGA devs out there than you seem to think. I think it has to do with the fact that a lot of people seem to think that FPGA firmware is software and should be programmed by software people. You're not, but it's not an entirely common thing. I think it's ridiculous that the vendors won't open up their bitstream formats so that people can do interesting things with their devices (for example, there are some REALLY COOL AI things you could do if you could dynamically program bits of it on the fly, but until someone opens up their bitstream format, that ain't happening). I blame the lawyers, mostly; I seriously doubt there's anything going on in the bitstream format that would give Altera's competitors a competitive edge in the marketplace if they studied it, but I've found it really difficult to convince IP lawyers of things like that. - Dave

I would like to see someone use Icarus Verilog as a base and write a synthesizer and fitter for discrete 7400 and 4000 series logic chips. Perhaps drop out an Eagle or KiCad set of board files as a result - optimized for area or latency. If I were only retired, that would be a fun project to try myself -Alan

On 04/25/2013 08:18 PM, David Riley wrote: I have to admit that my big hurdle isn't writing the implementation code, but rather writing GOOD verification/simulation code. It seems that no matter how thorough you think you were, there's always a gotcha somewhere that you didn't think of that rears its ugly head when you actually try to use the thing. Thank heavens that the stuff is RE-programmable... --Chuck

Dave McGuire wrote: And you don't have to actually register - by selecting the "browse svn" link and navigating to the "web_uploads" folder you can download the files ("mcpu-doc.pdf" and "mcpu.pdf" seem to be exactly the same) just fine. Of course, if someone responsible for the site reads this they might change this. Though I have been part of the opencores community since the begining, I do find it a bother to have to log in when I just want to take a quick look at some project's file. -- Jecel

On Thu, 26 Apr 2013, Dave McGuire wrote: I don't know! It not being open would mean you couldn't get anything. Needing to register...with a lot of the information collected seeming to be statistical, it doesn't seem to bad... -- Cory Smelosky http://gewt.net/ Personal stuff http://gimme-sympathy.org Experiments

On 04/26/2013 12:08 AM, Mouse wrote: It wasn't intended as such. Here: "If you don't want to type a few lines of gibberish to get the free stuff that you'd otherwise have to pay thousands, or tens of thousands of dollars for, then don't. Type the gibberish, pay the money, or do without." And as others have pointed out, you don't actually even need to register. "OH MY GOD I HAVE TO TYPE SOMETHING TO GET FREE STUFF, HURRRR!" So don't go get the free stuff, then. Good heavens. Some people get WAY too uppity about friggin' NOTHING. Hence: "Get over it". -Dave -- Dave McGuire, AK4HZ New Kensington, PA

On Apr 26, 2013, at 9:53 AM, Toby Thain <toby at telegraphics.com.au> wrote: Ah, but they're respected. In certain (powerful) circles. I think that was probably the point; they're despicable, but respected. I don't think OpenCores is despicable; they're about as close to something like SourceForge as you get with FPGA stuff. I don't think they have a license that they require you to use for projects (or at least they didn't a few years ago), so lots of projects are GPL or BSD licensed. GPL cores, obviously, present some issues when using them in commercial products, but most of the ones I've used are BSD or similar. - Dave

Exactly. They are, however, well-respected (in suitable circles, which is an equally necessary caveat for any such statement). I was citing them _because_ they are, as you put it, viciously proprietary - I was trying to point out that being "a very well-respected organization" is not particularly relevant to actual openness. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

On 26/04/13 12:49 PM, Mouse wrote: I see your intention now... Thanks for clarifying. --Toby

On Apr 25, 2013, at 7:45 PM, ben wrote: Compared to most IP cores, which come as binary, it's quite open. You have access to the full source code. Registration is a relatively small price to pay, IMO. No one uses AHDL. I'm frankly surprised it's still supported at all. I STRONGLY recommend you use either Verilog or VHDL if you want any hope at all of portability. Both schematic capture and weird, proprietary languages will tie you inexorably to a single vendor, and you don't want that. - Dave

On 4/25/2013 9:49 PM, David Riley wrote: Well I have been digging for information on using the DE0 board on the net. It seems to be TWO types of information. A) Use schematic entry for the push button switches. B) Use the latest bells and whistles to have everything auto compiled for you. What I am looking for is 1) Generic SDRAM interface with a 25 Mhz clock. 2) A Industry Standard Uart interface. 3) Generic flash controller interface. I don't see that around. Also a good generic POWER up reset circuit would be handy. Ben.

On 4/26/2013 5:54 PM, David Riley wrote: What ip core to use, is my problem. I guess I could order the DE1 board to replace the DE0. What was used in the PDP 11 setup I wonder. I am not sure what I can use nowdays, everthing is $$$ for the IP stuff. Is the static ram on the DE1 board easy to use? Ben.

On 4/26/2013 6:51 PM, Dave McGuire wrote: [head explodes] My head is doing that. Digging on the net is not providing useful information. I have the web edition of software, so having demo IP stuff is doing me no good. Ben. I am trying to find info on the altera forum, most of the messages all say use Qsys stuff. That would be ok but Altera had promotional stuff for the other FPGA hardware. I go nag at them, and then go shopping for food.

On 04/27/2013 12:24 AM, Bryan Pope wrote: thankyou -- Dave McGuire, AK4HZ New Kensington, PA

On 04/27/2013 01:18 AM, Cory Smelosky wrote: Yes, that would be must helpful, thank you. -Dave -- Dave McGuire, AK4HZ New Kensington, PA

On 27/04/2013 06:46, ben wrote: Sorry I don't spot. Thats why I bought the Nexys2 , becaise it as (pseudo) Static Ram...

On 27/04/2013 15:48, ben wrote: All these are documented in the data sheet for the 3e. I would expect the DE0 to be the same..... I always use explicit brackets so I can see at a glance. Its too easy to make a mistake other wise. This could be that I was damaged as a youth as the first "high Level Language" I was taught was Fortran II and that required explicit conversion between integer and real....

Just wanted to say this thread is great! I have a TerasIC Cyclone I board here that I am keen to play with, so all information about Altera and products is very helpful. I didn't know their Linux stuff was on par with Windows; last time I used Quartus it was on Windows XP (and Linux/WINE, even - with minor hiccups). The FPGA on my board is EP1C6Q240C8. --Toby

On 04/27/2013 03:10 PM, David Riley wrote: The Xilinx software was the same thing. Up until a few releases ago (7? maybe 8?) it was Windows software with a really bad API compatibility layer spackled on top. It was all but unusable. Now they have a real port, it's very nice and smooth. Pretty odd for software that started out in the UNIX world in the first place, and lived most of its life there! -Dave -- Dave McGuire, AK4HZ New Kensington, PA

On Saturday, April 27, 2013 17:24:56 Toby Thain wrote: When I started my pdp11 project, Altera's tools were awful - it produced plainly wrong results now and then, and Xilinx only ran on Windows - I used CVS to move between my editing machine and the build machine. Times have changed. Both vendors now produce decent toolchains on Linux - including the simulators, which have a steep learning curve maybe, but it's really nice stuff to play with. I still don't use either vendors built in editors, but that is a matter of preference rather than anything else - I happen to like KDE's kate very much. The only thing I have left to whine about is that Quartus does not understand about changing project files outside of what it does itself - it's internal make concept does not see any changes in project files. But I'm sure they'll get there eventually.

On Saturday, April 27, 2013 17:30:08 Toby Thain wrote: On the subject of the board, it is indeed REALLY small, I'd be surprised if it fits my pdp11 core - even when configured for very small models, like 11/03 or 11/10. Old in this case means 'no longer for sale' - or 'not recommended for new designs', which basically means the same. In other words, the mainstream of tooling is moving away from it, and support for the chip itself may no longer be in the latest versions. You can still get the older versions of the tooling though - so, supporting existing hardware is not a problem. I think this is already the case for first generation Cyclone chips like yours - I don't find support for it in my current version of Altera's Quartus. Does that stoke the arguments elsewhere? Certainly. But, those belong in a grey area anyway, it just hinges on where you put the bar. Designing hardware in VHDL does really form a special place in there, that nobody seems to recognize as such. Yes, the design I made for a pdp11 depends on the tooling from Altera or Xilinx to put into their FPGA's. But, I could also mail the VHDL files to a foundry and have them etch silicon for it. In both cases, I depend on the respective companies to use their IP to do something sensible to my design. But the design itself does not depend on a single company - but rather upon the status of VHDL as a standard. I don't think I made a wrong choice there... But, if in 10 or 20 years I'm unable to compile my VHDL in the then-standard tooling, be sure to remind me to eat my words.

On Apr 27, 2013, at 2:02 PM, Dave wrote: It's quite similar, which makes sense, since they do almost the same thing. :-) I've never had cause to manually re-route anything, though, and I've been at this a while. Programmable logic has HUGE advantages in implementing any kind of synthesized hardware like CPUs, VGA controllers, PCI interfaces, etc. They're really terrible tasks for CPUs; I'm constantly baffled at projects like the SwinSID, which use the GPIO port on a microcontroller to implement the 6502 bus interface. Such a waste of cycles, even if it is interrupt-driven! Conversely, though, there are plenty of things that a CPU is much more suitable for, specifically most things that are highly sequential. You wouldn't want to make a web server on an FPGA, for example, because you would need to make lots of complex state machines that would be really hard to debug. Fortunately, it's usually pretty easy to just bolt on a microcontroller (or build one in FPGA logic, because a CPU is really just a specialized state machine with some logic and registers bolted on). Both Xilinx and Altera have soft-core CPUs that are free to use and toolchains for them that aren't COMPLETE nightmares. - Dave

On Apr 27, 2013, at 3:35 PM, Dave wrote: Well, sometimes you have to fix things that the synthesis tool gets wrong. Sometimes you just need the extra performance; it's a lot like the situations in which you'd need to write assembly in software these days. There are actually a number of third-party synthesis tools that are commercially available; they synthesize the initial intermediate netlist that the manufacturer's tool can do the final mapping to a real device and fitting to said device. There are various reasons to do that; portability is a big one (not only between FPGA families, but also e.g. to ASICs), but performance is another. The netlists that come from the commercial synthesis tools can be somewhat faster or smaller than the ones from the manufacturers' tools; these days, though, at least Altera and Xilinx do pretty good synthesis. I know at least Icarus Verilog used to have a synthesis target, but my recollection is that it's been somewhat defunct for a while now (the synthesis target, not Icarus). All three of those are extremely cool. I need to get a Spartan 6 board now, I guess. :-) Oh, sure. No argument there. I'm just always surprised when people suggest making e.g. a VGA controller with an Arduino, because it seems like powering a boat with a motorcycle to me. Yeah, I don't retire for... a while now. It makes it hard to find the spare time, for sure. - Dave

On Saturday, April 27, 2013 14:41:17 ben wrote: Current hardware tends to stop at 3.3V. There is nothing stopping you from adding your own level convertors to raise that to 5V. Might be a bit difficult to make all the electrical bits conform to the original specs. Not in any way impossible, though. Yep. You can have an 11/94 for the price of a de0-nano, some wires, an r232 level shifter and an sd card. If you try hard enough, you can keep that under $100. And, you could also add the hardware you're thinking of interfacing to, inside the FPGA instead. In many cases, implementing the logic in the FPGA itself is not really that much harder than implementing the interface to the real hardware. Consider how I did the rs232 and disk controllers - somewhat complex, but probably easier than interfacing to the real hardware. Does the job, though. Someone posting to this list is over halfway there :-)

On 4/28/2013 7:39 AM, David Riley wrote: A quick glance at the DE0 schematic just shows direct connections to the headers. I made a quick choice with the DE0 hoping it would have all what I need. That was a bad choice on my part, from just reading the web site. The docs are there, but you have dig for them. None the less, both boards do make nice hardware for the classic machines. Ben.

On 4/28/2013 11:44 AM, David Riley wrote: I guessed when I bought the board One header would be IDE and the other a custom I/O. The SRAM will let me do crash and burn testing. Off hand the 18 bit cpu I am designing looks to have about 150 LE's for the alu and 150 for the registers. I am guessing about 300 more for the random control logic. What other fun projects?

My KS-10 FPGA is a work in progress. See: http://techtravels.org/?page_id=656 Rob.

On 27/04/13 3:05 PM, David Riley wrote: In the case of Altera Nios, I think that is gcc (+ Eclipse). --Toby

On a somewhat related(>) subject, has anyone used the ARM-based Cypress PSoC chips? They're kind of interesting in having a standard ARM core and a programmable logic part--and being able to use split power supplies to support 5V I/O, for example. Does anyone have any experience with these? They look to be a tad expensive. --Chuck

On Friday, April 26, 2013 23:46:52 ben wrote: DE1 has a somewhat smallish sram - 512Kb. Enough for most of DEC's operating systems, but limiting if you want to run 2.11BSD with the networking stuff and ethernet - I doubt if it will run at all. There's sdram on DE1 as well, but I'm having problems with it - probably I'm missing something. Or maybe my board is flawed - ehh, I doubt that is really the problem. sram is much easier to interface, that's certainly true. However, I learned that sdram is easy enough as well, as long as you are not trying for optimal bandwidth or using all banks simultaneously. The timing is still a lot more involved though. But then, you could also consider that any decent FPGA has internal srams - both the FPGA's on DE1 and DE0 have. Smaller, certainly - but, if you need a 4K sram, it's there. So it really comes down to what you need the memories for.

On 25/04/2013 00:32, ben wrote: I started here:- http://cosmiac.org/Projects_FPGA.html & here http://cosmiac.org/spartan3e_tutorials.html but these are Xilynx specific, although the tools look very similar to the Quartus II software... I would run through the tutorials from Altera and then ask again about the specifics you need more info on. There is a load of free stuff on their web site similar to the cosmiac sites. http://www.altera.co.uk/education/univ/materials/manual/unv-lab-manual.html Much is designed around the Quartus II tool for which there is a free web edition for your chip/board. So if you use these tutorials and the web edition software you should be able to concentrate on learning Verilig or VHDL (or implementing using schematics) ... There will probably be sample designs of the web site. You may also find usefull things on the "opencores.org" . There is also an FPGA usenet group and a Yahoo group. Both are very quiet but with good stuff ion the archives. You need to decide if you are going to do a "high level" functional spec base implementation which I would recommend to start with, or a "gate perfect" implementation, which is much closed to the original spec, but will take much longer. I hope the answers are clear. Sorry for the delay but here in East Pondia I sleep when you are all come out to play in West Pondia... -- Dave Wade G4UGM Illegitimi Non Carborundum

For me also its the hardware that I get the most pleasure outoff. Pouring over the drawings/scope/La for houres to find out exactly what ic is cousing the ISZ to not skip, or wher the middle 4 bits of the AC have gone to is the fun bit and the sence of achivement when you first see the os8 dot promt on a 40 year old 8 is hard to beat. Quite waht i will do when I get everything fixed i dont know but thats a long way of yet ( MTBF 1 week and rising )! DaveH ----- Original Message ----- From: "Tony Duell" <ard at p850ug1.demon.co.uk> To: <cctalk at classiccmp.org> Sent: Sunday, April 14, 2013 9:23 PM Subject: Re: Hardware vs Simh

On Apr 14, 2013, at 2:47 PM, Mouse <mouse at rodents-montreal.org> wrote: Oh, that absolutely exists, pretty much for that exact purpose. http://www.comwaretech.com/PDP-11/DEC-PDP-11-emulator.html Probably expensive as hell, but it's meant for people who need the existing hardware to work because the cost or other risk of engineering a replacement system is even greater. - Dave

actually, I suspect that the total amount I have spent on my real DEC PDP11s over the years (getting the machines, buying spares, etc) has eben a lot less than the amount I would have spent on `repairing' (boarfswapping) and upgrading a PC over that time. I cna think of reasons ot ru nthe real hardaware. The first is the obvious one that you jsut enjoy it. I can think of a do0zne things that otehr people do and enjoy that I personally would hate. But that doesn't mean I think they're wrogn to do said things. The seocnd is that the real hardware does let yuou do things -- and learn things -- that the simualtor does not. Th third is that there may be some peripheral for the real hardare that cannot be simuated, or that the simualtor does not support.My 11/45 systme has multiple ADCs, DACs, user ports, etc. Now, such thigns are availabel for PCs, I know, but I didn't think that SimH supported them. Maybe I am wrong, does it provide senible emulators of an AD11-K, an AA11-K, etc? -tony

On 04/14/2013 12:34 PM, Jim Stephens wrote: Understandable. I, however find failures in older gear fascinating...you can actually fix them a lot of the time. ;) They're also a great learning experience as you can actually get at the components! I just like a challenge, a broken system that I can get at makes me think. -- Cory Smelosky http://gewt.net Personal stuff http://gimme-sympathy.org Experiments

On 14 Apr 2013, at 16:06, "Tony Duell" <ard at p850ug1.demon.co.uk> wrote: Exactly! You can actually get at the individual parts! Everything isn't 200% integrated. ;) Very interesting! I don't have too much low-level hardware knowledge (yet. I intend to! I'm still young.) but that still sounds extremely fun. Yeah. Fixing the problem is a large part of the fun. ;) I don't mind fixing the occasional software problem too though. ;)

On 04/15/2013 03:24 PM, Tony Duell wrote: Yeah, finding a custom ASIC for a modern PC is damn near utterly impossible. ;) You can get at more components than a modern PC though but yeah, your point about an older UNIBUS system for that is correct. ;) Interesting! I could probably do the same with the right knowledge and enough time! -- Cory Smelosky http://gewt.net Personal stuff http://gimme-sympathy.org Experiments

Of course you can. There's no real magic involved. Just a lot of practice (at least in my case). But if you want to learn and are prepared to spend time learning, then you can do it too. -tony

On 04/14/2013 03:55 PM, allison wrote: Nope...11/53 is a J11 on a *completely different* CPU board, which includes onboard memory. -Dave -- Dave McGuire, AK4HZ New Kensington, PA

I asusme that you mean that there is a single PCB containing the proceessor and memory. For PDP11s, I would guess the first was the original LSI11. It had 4K (IIRC) of RAM o nthe processor board. All older PDP11s weren't even single-board processors. For other machines, I would guess one of the microprocessor evaluation boards was the first to hae the CPU chip and memroy on one PCB. -tony

On 04/15/2013 06:01 AM, allison wrote: Well, YOU do. ;) I nod to your vast DEC experience and former employment, but I do have a bit myself. "11/53 as a system designator" is open to interpretation, IMO. What other machines were KDJ11-D boards used in, for example? Except, of course, for the DECserver-500 and -550, but that "barely" counts, as the ROMs are different. There's also the bizarreness over "what constitutes an 11/83"...is it 18MHz vs. 15MHz, or PMI vs. non-PMI? Most (all?) quad-wide 15MHz KDJ11-B boards support PMI memory, so the distinction can't just be "supports PMI"...but howabout "populated with PMI?" It's not just 15MHz vs. 18MHz, as very late 11/73s shipped with 18MHz CPUs. DEC didn't always do things consistently, and they didn't always follow their own rules. I have one of those here, not in the pedestal shroud though; it's in a rack. I like that system a lot; it's running RSTS/E v10.1 on an RD54 with a TSV05. There's also a BA11-SA labeled "PDP-11/23 PLUS". Same here. -Dave -- Dave McGuire, AK4HZ New Kensington, PA

On Mon, Apr 15, 2013 at 3:01 AM, allison <ajp166 at verizon.net> wrote: Would a system with an M8189 KDF11-B CPU module really ever be called a PDP-11/53 instead of a PDP-11/23? Or would a system only ever be called a PDP-11/53 when it has an M7554 KDJ11-D CPU module, or also maybe with an M7554 KDJ11-S with the appropriate firmware?