30 Sep
2010
30 Sep
'10
4:23 p.m.
I just sold 30# of aluminum heatsink approx 8"
wide x 4" high x 5' long for
$40.00. 9 other identical pieces were scrapped out for about $15.00 each. My
understanding is that they were in the $100.00 + catagory when new.
And that sounds like it was for stock extrusions. If you add all sorts
of machining so the heatsink actually touches the processor, you can
add a bunch more on to the price.
Fans are cheap and effective.
And the last place *anyone* wants to go is liquid cooling.
--
Will
1 Oct
1 Oct
12:11 p.m.
William Donzelli wrote:
I was just thinking how many other sources of noise I have in my home -
microwave, washing machine, dishwasher, clothes drier, fridge etc. and how
people don't typically complain about the noise that they make.
That's because we don't generally sit right next to them, so maybe that's the
issue with current computers - not the noise they make, but the fact that it's
intrusive because it's right next to us for extended periods.
Maybe the solution isn't to make PCs quiet, but simply to get them out of the
darn way :-)
cheers
Jules
I just sold
30# of aluminum heatsink approx 8" wide x 4" high x 5' long for
$40.00. 9 other identical pieces were scrapped out for about $15.00 each. My
understanding is that they were in the $100.00 + catagory when new.
And that sounds like it was for stock extrusions. If you add all sorts
of machining so the heatsink actually touches the processor, you can
add a bunch more on to the price.
Fans are cheap and effective. 
1:08 p.m.
New subject: Ones' complement adder/subtractor
I've seen a little discussion of ones'complement (or "compliment if
you're a recent graduate of the US university system) on the EDA
fora, with no satisfactory resolution of the end-around carry
stability issue.
Given that almost every CPU that I've seen since 1980 has operated in
two's complement, I submit that this qualifies as a "classic"
discussion.
I can't seem to derive a stable expression (Verilog) for adding two
numbers, A and B,in ones' complement without computing A+B and A+B+1
as a two's complement adder and then selecting one or the other
result depending on the carry-out. This seems to me to be a huge
waste of logic.
Has anyone in their FPGA simulations ever run into this one and come
up with a clever solution?
Just curious,
Chuck
6:37 p.m.
New subject: Ones' complement adder/subtractor
--- On Fri, 10/1/10, Chuck Guzis <cclist at sydex.com> wrote:
I can't seem to derive a stable expression
(Verilog) for
adding two
numbers, A and B,in ones' complement without computing A+B
and A+B+1
as a two's complement adder and then selecting one or the
other
result depending on the carry-out.? This seems to me
to be a huge
waste of logic.
I am not sure exactly what you mean by a "stable expression", but I presume that
your difficulty is in coming up with a purely combinational formulation of the end-around
carry, suitable for execution in a single cycle, that seems suitably economical in logic.
I'm wondering if, historically, the situation was any better in hardwired logic. It
was common in those days to do carry propagation in a second cycle (minor cycle, clock
phase). This allowed such tricks as using a gated toggle input on the accumulator
flip-flops as an XOR/accumulate, to implement the XOR part of a half-adder. This was even
done for 2's complement.
--Bill
7:16 p.m.
New subject: Ones' complement adder/subtractor
On 1 Oct 2010 at 18:37, William Maddox wrote:
I am not sure exactly what you mean by a "stable
expression", but I
presume that your difficulty is in coming up with a purely
combinational formulation of the end-around carry, suitable for
execution in a single cycle, that seems suitably economical in logic.
Exactly--if you take a simple adder and send the carry-out to the
carry-in, you wind up with a race condition. You could clock the
circuit and run a second addition/increment based on the presence of
carry-out, but then you've got a synchronous adder with a delay of
either one or two clocks. If you're after an adder that operates
either asynchronously or synchronously in a specific number of
clocks, you have to settle for 2 clocks--one clock seems not to be
possible.
I've been doing some research since my post and patent 4,298,952 uses
ancillary logic to generate a carry-lookahead signal independent of
the adder. I'm not sure if this accomplishes much.
The other patent I can find on the subject is essentially the scheme
that I first described--compute two sums and then select the
appropriate one--is 6,343,306, published in (surprisingly) 2002 and
assigned to Sun.
Another is 4,099,248, from 1978, that describes a substractive adder,
such as used in the older CDC gear (minimizes the problem of negative
zero), but implemented with 10K ECL logic blocks.
This one's been scratching at my brain for some time and I wondered
if anyone had any background on it.
Thanks,
Chuck
9:28 p.m.
New subject: Ones' complement adder/subtractor
On 01/10/2010 8:16 PM, Chuck Guzis wrote:
On 1 Oct 2010 at 18:37, William Maddox wrote:
what race condition? Here I am thinking of simple ripple adder.
if you have no carry out, no problem.
if you have a carry, the carry must stabilize before you
have the start of the carry out propagate.
so a 1x delay is needed as the back of the envelope calculations.
Off hand I can't think of what gives over flow, the more important thing.
I am not sure exactly what you mean by a
"stable expression", but I
presume that your difficulty is in coming up with a purely
combinational formulation of the end-around carry, suitable for
execution in a single cycle, that seems suitably economical in logic.
Exactly--if you take a simple adder and send the carry-out to the
carry-in, you wind up with a race condition. You could clock the
circuit and run a second addition/increment based on the presence of
carry-out, but then you've got a synchronous adder with a delay of
either one or two clocks. If you're after an adder that operates
either asynchronously or synchronously in a specific number of
clocks, you have to settle for 2 clocks--one clock seems not to be
possible.
Thanks,
Chuck
9:50 p.m.
New subject: Ones' complement adder/subtractor
On 1 Oct 2010 at 22:28, ben wrote:
what race condition? Here I am thinking of simple
ripple adder.
See the following paper:
http://crc.stanford.edu/crc_papers/Shedletsky_cos.pdf
--Chuck
2 Oct
2 Oct
12:10 a.m.
New subject: Ones' complement adder/subtractor
On 01/10/2010 10:50 PM, Chuck Guzis wrote:
On 1 Oct 2010 at 22:28, ben wrote:
Why? I was thinking of it
on-line when I read the message.
I'll stick to real gates, rather than the fictional gates
you play with today.
what race condition? Here I am thinking of simple
ripple adder.
See the following paper:
http://crc.stanford.edu/crc_papers/Shedletsky_cos.pdf --Chuck
Ben.
Who is up working on hardware I always wanted to build,
now writing the microcode at the wee hours of the morning.
9:50 a.m.
New subject: Ones' complement adder/subtractor
On 10/01/2010 07:16 PM, Chuck Guzis wrote:
patent 4,298,952 uses
ancillary logic to generate a carry-lookahead signal independent of
the adder. I'm not sure if this accomplishes much.
It does exactly what you've asked for. The point of it is that if
you're using off-the shelf parts, or off-the-shelf standard cells in an
ASIC, you already can get adders with the carry lookahead logic. In an
FPGA you don't, so the dual-adder design you described (and Sun
patented) will generally have lower resource utilization and be faster.
Eric
10:28 a.m.
New subject: Ones' complement adder/subtractor
On 02/10/2010 10:50 AM, Eric Smith wrote:
On 10/01/2010 07:16 PM, Chuck Guzis wrote:
Then again watch the hardware, a FPGA with fast hardware ripple carry
may do something sneaky to the logic.
patent 4,298,952 uses
ancillary logic to generate a carry-lookahead signal independent of
the adder. I'm not sure if this accomplishes much.
It does exactly what you've asked for. The point of it is that if you're
using off-the shelf parts, or off-the-shelf standard cells in an ASIC,
you already can get adders with the carry lookahead logic. In an FPGA
you don't, so the dual-adder design you described (and Sun patented)
will generally have lower resource utilization and be faster. Eric
Ben,who is back to designing on paper since I can't find a
ISB jtag cable here in Canada.
1:19 p.m.
New subject: Ones' complement adder/subtractor
Ben wrote:
Then again watch the hardware, a FPGA with fast
hardware ripple carry
may do something sneaky to the logic.
It might use carry-lookahead internally, but it doesn't give you access
to generate and propagate outputs, so if you want those you'll have to
do it yourself. That makes the Honeywell approach generally less suited
to FPGA use.
Eric
11:04 a.m.
New subject: Ones' complement adder/subtractor
On 2 Oct 2010 at 9:50, Eric Smith wrote:
It does exactly what you've asked for. The point
of it is that if
you're using off-the shelf parts, or off-the-shelf standard cells in
an ASIC, you already can get adders with the carry lookahead logic.
In an FPGA you don't, so the dual-adder design you described (and Sun
patented) will generally have lower resource utilization and be
faster.
Why the Sun patent doesn't qualify as "prior art" is beyond me. But
the patent system is "grant first, litigate later", so it figures.
I'll probably end up doing a 2-stage/2-clock adder-followed-by-
incrementer. At least it's straightforward.
Thanks,
Chuck
11:52 a.m.
New subject: Ones' complement adder/subtractor
Chuck wrote:
Why the Sun patent doesn't qualify as "prior
art" is beyond me.
I'm confused. Which patent are you saying should qualify as prior art?
The Sun patent is fairly recent, so it can't qualify as prior art with
respect to the older patents we've mentioned.
Eric
12:23 p.m.
New subject: Ones' complement adder/subtractor
On 2 Oct 2010 at 11:52, Eric Smith wrote:
I'm confused. Which patent are you saying should
qualify as prior art?
The Sun patent is fairly recent, so it can't qualify as prior art with
respect to the older patents we've mentioned.
It's hard to believe that the approach used in the Sun patent hadn't
been used commercially before. That's what I meant by "prior art".
--Chuck
12:50 p.m.
New subject: Ones' complement adder/subtractor
Chuck wrote:
It's hard to believe that the approach used in the
Sun patent hadn't
been used commercially before. That's what I meant by "prior art".
In patent-speak, what you mean is that you're surpised that there isn't
some earlier commercial development which qualifies as prior art to
invalidate the Sun claims. The Sun patent can only be prior art for
things that come after it.
Eric
1:27 p.m.
New subject: Ones' complement adder/subtractor
On 2 Oct 2010 at 12:50, Eric Smith wrote:
In patent-speak, what you mean is that you're
surpised that there
isn't some earlier commercial development which qualifies as prior art
to invalidate the Sun claims. The Sun patent can only be prior art for
things that come after it.
I misspoke--that's what I meant.
--Chuck
4:49 p.m.
New subject: Ones' complement adder/subtractor
From: eric at brouhaha.com
On 10/01/2010 07:16 PM, Chuck Guzis wrote:
Hi
Another possible is to put an incrementor on the output. This
is a simpler circuit than a full adder.
Dwight
patent 4,298,952 uses
ancillary logic to generate a carry-lookahead signal independent of
the adder. I'm not sure if this accomplishes much.
It does exactly what you've asked for. The point of it is that if
you're using off-the shelf parts, or off-the-shelf standard cells in an
ASIC, you already can get adders with the carry lookahead logic. In an
FPGA you don't, so the dual-adder design you described (and Sun
patented) will generally have lower resource utilization and be faster.
Eric
5:30 p.m.
New subject: Ones' complement adder/subtractor
Dwight wrote:
Another possible is to put an incrementor on the
output.
This is a simpler circuit than a full adder.
In "discrete" logic, or in an ASIC, it is simpler.
In most FPGAs, it will end up taking the same resources and having the
same performance as a full-adder.
Eric
7:23 p.m.
New subject: Ones' complement adder/subtractor
From: eric at brouhaha.com
Dwight wrote:
Hi
Half area but just as long in time.
Dwight
Another possible is to put an incrementor on the
output.
This is a simpler circuit than a full adder.
In "discrete" logic, or in an ASIC, it is simpler.
In most FPGAs, it will end up taking the same resources and having the
same performance as a full-adder.
Eric
7:45 p.m.
New subject: Ones' complement adder/subtractor
Dwight wrote:
Another possible is to put an incrementor on the
output.
This is a simpler circuit than a full adder.
I wrote:
> In "discrete" logic, or in an ASIC, it
is simpler. In most FPGAs, it
> will end up taking the same resources and having the same performance
> as a full-adder.
Dwight wrote:
Half area but just as long in time.
Same area
in FPGA, not half. Almost all FPGAs use LUTs with four or
more inputs, and half-adders generally end up taking a full LUT, just as
a full-adder does. The exception would be when the incrementer
(half-adders) could be merged with the previous stage of logic, but when
the incrementer follows a full-adder, you can't merge them, because they
each need a separate carry chain.
Eric
8:45 p.m.
New subject: Ones' complement adder/subtractor
From: eric at brouhaha.com
Dwight wrote:
Haaa! Evil FPGA!
Would it be possible to put two half adders in a single LUT?
Dwight
Another possible is to put an incrementor on the
output.
This is a simpler circuit than a full adder.
I wrote:
> In "discrete" logic, or in an ASIC,
it is simpler. In most FPGAs, it
> will end up taking the same resources and having the same performance
> as a full-adder.
Dwight wrote:
Half area but just as long in time.
Same
area in FPGA, not half. Almost all FPGAs use LUTs with four or
more inputs, and half-adders generally end up taking a full LUT, just as
a full-adder does. The exception would be when the incrementer
(half-adders) could be merged with the previous stage of logic, but when
the incrementer follows a full-adder, you can't merge them, because they
each need a separate carry chain.
Eric
9:06 p.m.
New subject: Ones' complement adder/subtractor
Dwight asks:
Haaa! Evil FPGA!
Would it be possible to put two half adders in a single LUT? Dwight
Generally not. Traditional Xilinx FPGAs, such as the Virtex-4 and
Spartan-3 families, use a logic element that consists of a 4-LUT
(four-input Look-Up Table) and a flip-flop. (You don't have to use the
flip-flop.) There are some added complications such as the dedicated
carry logic chain. The 4-LUT is a 16-word 1-bit RAM, and gets loaded
when the FPGA is configured. It can generate a single boolean function
of up to four inputs.
The reason I say "generally not" is that recent Xilinx FPGAs, such as
the Virtex-5, Virtex-6, and Spartan-6, use what Xilinx calls a 6-LUT,
with two flip-flops. This can be used as two 5-LUTs to generate two
functions of five inputs, provided that the same five inputs are shared
between both functions. You actually could put two half-adders into one
of these 6-LUTs, if you didn't want to take advantage of the dedicated
carry logic chain. However, the dedicated carry logic chain is much
faster than the usual through-the-fabric routing, so if you need your
one's complement adder to have high performance, you won't want to do it
that way.
Eric
1 Oct
1 Oct
7:01 p.m.
New subject: Ones' complement adder/subtractor
Chuck Guzis wrote:
I can't seem to derive a stable expression
(Verilog) for adding two
numbers, A and B,in ones' complement without computing A+B and A+B+1
as a two's complement adder and then selecting one or the other
result depending on the carry-out. This seems to me to be a huge
waste of logic.
Has anyone in their FPGA simulations ever run into this one and come
up with a clever solution?
Umm... the use of two adders and a mux *IS* the clever
solution. Unless
you're going to have a large array of one's complement adders for some
reason, the resource utilization will be in the noise. It is also
generally faster than most (if not all) other ways of implementing one's
complement addition.
Unfortunately Sun managed to patent this in 1999, despite it having been
common practice for many years. US patent number 6,343,306. I haven't
tried to find specific prior art, but I recall seeing it done that way
in the early 1980s.
The other clever way to do it, if you happen to have a two's complement
adder that has a Generate output for carry lookahead (which you won't
have in an FPGA, unless you implement it yourself), is to tie the
Generate output to the carry input. Honeywell had a patent on that, now
expired: US 4,298,952.
Eric
2 Oct
2 Oct
5:02 a.m.
New subject: Ones' complement adder/subtractor
On Fri, Oct 1, 2010 at 4:08 PM, Chuck Guzis <cclist at sydex.com> wrote:
I can't seem to derive a stable expression (Verilog) for adding two
numbers, A and B,in ones' complement without computing A+B and A+B+1
as a two's complement adder and then selecting one or the other
result depending on the carry-out. This seems to me to be a huge
waste of logic.
that's been the problem with FPGA synthesis all along, they've never been
more than average at best
as they always say, when in doubt, instantiate ! ;)
=Dan
--http://www.vintagecomputer.net/ragooman/
5194
days inactive
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26 comments
9 participants
participants (9)
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bfranchuk＠jetnet.ab.ca -
cclist＠sydex.com -
cisin＠xenosoft.com -
dkelvey＠hotmail.com -
eric＠brouhaha.com -
jules.richardson99＠gmail.com -
ragooman＠gmail.com -
wdonzelli＠gmail.com -
wmaddox＠pacbell.net