16 Jul
2014
16 Jul
'14
1:49 p.m.
Basically, my question is what are the major obstacles (besides the breadth
of the project) to implementing the VAX in an FPGA, as compared to any
other ISA?
16 Jul
16 Jul
1:58 p.m.
On Jul 16, 2014, at 1:49 PM, Kevin Keith <krfkeith at gmail.com> wrote:
Basically, my question is what are the major obstacles
(besides the breadth
of the project) to implementing the VAX in an FPGA, as compared to any
other ISA?
You?d have to design an I/O model that the existing OSs support, or adjust the OS code to
fit your I/O model.
Apart from that, and as you point out the size of the effort, it actually helps a lot that
the architecture is quite consistent and well documented. The Architecture manual spells
out what each instruction does, and what all the other major blocks do, in a lot of detail
and with substantial rigor.
You might start with a PDP-11 as a warmup exercise ? that has the same advantages but the
I/O issue is way smaller and so is the overall scope.
paul
2:19 p.m.
On Jul 16, 2014, at 1:58 PM, Paul Koning <paulkoning at comcast.net> wrote:
On Jul 16, 2014, at 1:49 PM, Kevin Keith <krfkeith at gmail.com> wrote:
Indeed; the first option is generally way easier. To get started, the console
SLU is actually pretty simple hardware; you could get basic processor booting
with that. Further devices increase significantly in complexity; for any MSCP
devices, you almost certainly want some sort of processor running, but basic
SCSI chips like those used in early VAXstations aren't so bad (I think a lot
of the early 3100s used the 53C80, which is dead simple because it's mostly
just a buffer).
A console SLU and an appropriate boot ROM (assuming you're implementing a
particular CPU bug-for-bug) will actually get you a lot of the way.
Everything else is an optional peripheral, for varying definitions of the
word "optional". :-)
- Dave
Basically, my question is what are the major
obstacles (besides the breadth
of the project) to implementing the VAX in an FPGA, as compared to any
other ISA?
You?d have to design an I/O model that the existing OSs support, or adjust the OS code to
fit your I/O model.
6:22 p.m.
On 16 July 2014 11:58, Paul Koning <paulkoning at comcast.net> wrote:
You?d have to design an I/O model that the existing OSs support, or adjust
the OS code to fit your I/O model.
I was afraid of that! It seems most/a lot FPGA-based vintage computer
recreation projects get stuck at the I/O stage.
Apart from that, and as you point out the size of the
effort, it actually
helps a lot that the architecture is quite consistent and well documented.
The Architecture manual spells out what each instruction does, and what
all the other major blocks do, in a lot of detail and with substantial
rigor.
Yes! That is *definitely* helpful! I've been reading through DEC Standard
032, which has been immensely useful.
You might start with a PDP-11 as a warmup exercise ? that has the same
advantages but the I/O issue is way smaller and so is
the overall scope.
Well, not quite the same, but I've reading through the various open-source
PDP-11 implementations out there. Unfortunately, the one on OpenCores
wasn't too useful, as it is a hardwired design, which isn't really feasible
to do for a VAX.
Thanks for your suggestions!
2:04 p.m.
On Jul 16, 2014, at 1:49 PM, Kevin Keith <krfkeith at gmail.com> wrote:
Basically, my question is what are the major obstacles
(besides the breadth
of the project) to implementing the VAX in an FPGA, as compared to any
other ISA?
I would think breadth alone is enough. Not so much to make it infeasible,
but enough to take a long time to get there. VAX is an extremely complex
instruction set, but a lot of it is accomplished through microcode. The
CPU design is actually pretty cleanly divided up into boxes that fulfill
various architectural features; I'd suggest reading the Digital Technical
Journal articles on the design and implementation of NVAX as a primer.
If you're interested in starting a project, I'm somewhat interested in
contributing, as it's something I've had on my mind for a long time. I
don't have a lot of free time these days, but I may in the not-too-distant
future.
Making a wild-ass guess, with careful design, you could probably run
something at least as fast as a KA650 (CVAX) on even a cheap modern FPGA.
But that's a wholly uninformed guess; it could be either way faster or
way slower.
- Dave
4:11 p.m.
On 2014-07-16 12:04, David Riley wrote:
Making a wild-ass guess, with careful design, you
could probably run
something at least as fast as a KA650 (CVAX) on even a cheap modern FPGA.
But that's a wholly uninformed guess; it could be either way faster or
way slower.
It should be possible to catch up to a NVAX, but it probably is on
really modern low cost FPGAs.
But, probably we will see?
;-)
Cheers
5:53 p.m.
On Wed, Jul 16, 2014 at 02:11:26PM -0600, emanuel stiebler wrote:
On 2014-07-16 12:04, David Riley wrote:
> Making a wild-ass guess, with careful design, you could probably run
> something at least as fast as a KA650 (CVAX) on even a cheap modern FPGA.
> But that's a wholly uninformed guess; it could be either way faster or way
> slower.
It should be possible to catch up to a NVAX, but it
probably is on
really modern low cost FPGAs.
Thar Interwebs tells me that the KA650 has roughly 2.5 VUPs, with a VUP
equvalent to the bog standard 1977-vintage VAX 11/780, and further that the
11/780 ran at 5MHz and the superficial design elements seem similar to a CPU I
am more familiar with, the 68000. The VAX has paging hardware -- the giveaway
is in the acronym! -- which makes it a bit more complex, but we're still in the
same sort of ballpark.
So, here's a soft 68000: https://github.com/alfikpl/ao68000
The README.md notes that it has similar IPC to the 68000, is good for up to
about 82MHz, and uses roughly 5,000 LEs and 46kb of memory. I reckon this means
you could get four VAX cores onto the relatively low-specced Cyclone IV that
comes on the dirt cheap DE0-Nano FPGA dev kit.
The NVAX is 80-90MHz which is pleasingly similar to the maximum speed of that
68000 core. Did you fancy a cluster of four NVAXen that runs on a chip that
costs something like $15 in bulk and can be powered by a lemon with a couple of
nails banged into it?
6:28 p.m.
On Jul 16, 2014, at 5:53 PM, Peter Corlett wrote:
Thar Interwebs tells me that the KA650 has roughly 2.5
VUPs, with a VUP
equvalent to the bog standard 1977-vintage VAX 11/780, and further that the
11/780 ran at 5MHz and the superficial design elements seem similar to a CPU I
am more familiar with, the 68000. The VAX has paging hardware -- the giveaway
is in the acronym! -- which makes it a bit more complex, but we're still in the
same sort of ballpark.
So, here's a soft 68000: https://github.com/alfikpl/ao68000
The README.md notes that it has similar IPC to the 68000, is good for up to
about 82MHz, and uses roughly 5,000 LEs and 46kb of memory. I reckon this means
you could get four VAX cores onto the relatively low-specced Cyclone IV that
comes on the dirt cheap DE0-Nano FPGA dev kit.
The NVAX is 80-90MHz which is pleasingly similar to the maximum speed of that
68000 core. Did you fancy a cluster of four NVAXen that runs on a chip that
costs something like $15 in bulk and can be powered by a lemon with a couple of
nails banged into it?
You should be able to get that frequency out of it, but I doubt
you'd get the same performance per clock that you would out of
an NVAX (at least not without committing an awful lot of area).
NVAX had some really neat, sophisticated macropipelining and
other interesting ILP features that popped up right at the end
of the CISC CPU era (x86 notwithstanding, since they did a bit
of an end run around the CISC concept).
The (original) 68000, in contrast, is actually a really simple
design based around a 16-bit ALU and a piss-poor bus interface
unit with no bursting. I imagine if you implemented the
architectural features of, say, a 68040 in an FPGA, that you'd
run up the area quite a bit even without the monstrous FPU.
Still, going back to VAX-land, I'll bet you could get something
in between an NVAX and a CVAX, performance-wise, out of a
Cyclone IV without really blowing the utilization out of the
water. I'm definitely interested in contributing to such a
project, and I do FPGA design at all levels of performance and
cost as my dayjob.
- Dave
7:13 p.m.
The NVAX is an *amazingly* well done design. IIRC, it even has a limited
form of Out-of-order execution similar to the CDC 6600. Nevertheless, it
also was very complicated and is definitely beyond the scope of this
project. There are a few open FPU cores floating around, although adapting
them to use VAX floating point format might be rather difficult.
Anyway, concerning an 11/780 reimplementation, it might be best to leave
out a few of the more complicated things. Probably the MicroVAX instruction
subset might be a good place to start. Compatibility mode, in particular,
is probably not really worthwhile to leave in.
On 16 July 2014 16:28, David Riley <fraveydank at gmail.com> wrote:
On Jul 16, 2014, at 5:53 PM, Peter Corlett wrote:
--
Thanks,
Kevin
Thar Interwebs tells me that the KA650 has
roughly 2.5 VUPs, with a VUP
equvalent to the bog standard 1977-vintage VAX 11/780, and further that
the
11/780 ran at 5MHz and the superficial design
elements seem similar to a
CPU I
am more familiar with, the 68000. The VAX has
paging hardware -- the
giveaway
is in the acronym! -- which makes it a bit more
complex, but we're still
in the
same sort of ballpark.
So, here's a soft 68000: https://github.com/alfikpl/ao68000
The README.md notes that it has similar IPC to the 68000, is good for up
to
about 82MHz, and uses roughly 5,000 LEs and 46kb
of memory. I reckon
this means
you could get four VAX cores onto the relatively
low-specced Cyclone IV
that
comes on the dirt cheap DE0-Nano FPGA dev kit.
The NVAX is 80-90MHz which is pleasingly similar to the maximum speed of
that
68000 core. Did you fancy a cluster of four
NVAXen that runs on a chip
that
costs something like $15 in bulk and can be
powered by a lemon with a
couple of
nails banged into it?
You should be able to get that frequency out of it, but I doubt
you'd get the same performance per clock that you would out of
an NVAX (at least not without committing an awful lot of area).
NVAX had some really neat, sophisticated macropipelining and
other interesting ILP features that popped up right at the end
of the CISC CPU era (x86 notwithstanding, since they did a bit
of an end run around the CISC concept).
The (original) 68000, in contrast, is actually a really simple
design based around a 16-bit ALU and a piss-poor bus interface
unit with no bursting. I imagine if you implemented the
architectural features of, say, a 68040 in an FPGA, that you'd
run up the area quite a bit even without the monstrous FPU.
Still, going back to VAX-land, I'll bet you could get something
in between an NVAX and a CVAX, performance-wise, out of a
Cyclone IV without really blowing the utilization out of the
water. I'm definitely interested in contributing to such a
project, and I do FPGA design at all levels of performance and
cost as my dayjob.
- Dave
17 Jul
17 Jul
7:57 p.m.
On Wed, Jul 16, 2014 at 05:13:24PM -0600, Kevin Keith wrote:
There are a few open FPU cores floating around,
although adapting
them to use VAX floating point format might be rather difficult.
In the early days of microprocessors, FPUs were a large enough chunk of
circuitry that sometimes it was only feasible to have it as a coprocessor --
and fallback to software emulation if it wasn't found.
If I were to undertake such a project, that's the way that I would go.
I suppose it depends on how "authentic" you really want to be :-)
And, a big hack around dealing with I/O would be just to read and write data
to a memory space shared with a host PC. I have an ISA bus prototype card
sitting around (unused of course!), I don't know if there are such things
for modern PC busses.
But clearly you have to have the front panel :-)
One dream project would be to have a (replica?) PDP-11/20 front panel
hung on the wall, fully operational with Xilinx + flash (for its code) +
an SD card to emulate the core.
Anyways, that's what I would do if I had the time, and remembered
whatever I did with Xilinx stuff 20+ years ago.
mcl
p.s. if anyone *has* an 11/20 for sale, please contact me off-list :-)
It was my second "hands-on" marchine.
p.p.s. yes, I *am* that old.
18 Jul
18 Jul
4:56 a.m.
On 7/17/2014 4:57 PM, Mark Linimon wrote:
Most of the DEC 36-bit machines use the normal integer ALU to calculate
the floating-point mantissa. They add a little 10-bit ALU on the side
called the "SCAD" to calculate the floating-point exponent.
For example, floating-point normalization requires shifting the mantissa
while incrementing (or decrementing) the exponent.
The VAX 11/780 (without the floating-point accelerator) is similar but
calls the 10-bit exponent ALU the "EALU".
There really isn't much additional circuitry to implement hardware
floating-point.
Of course if you want /fast/ floating-point, you can add as much
hardware as you can afford...
Rob.
On Wed, Jul 16, 2014 at 05:13:24PM -0600, Kevin Keith
wrote:
> There are
a few open FPU cores floating around, although adapting
> them to use VAX floating point format might be rather difficult.
In the early days of microprocessors, FPUs were a large enough chunk
of circuitry that sometimes it was only feasible to have it as a
coprocessor -- and fallback to software emulation if it wasn't
found. 
11:45 a.m.
On Thu, 17 Jul 2014, Mark Linimon wrote:
One dream project would be to have a (replica?)
PDP-11/20 front panel
hung on the wall, fully operational with Xilinx + flash (for its code) +
an SD card to emulate the core.
Is the room on the other side of the wall large enough to hold the back
end of a moose?
16 Jul
16 Jul
6:39 p.m.
Well, my goal is an 11/780. As others have pointed out, it appears to be
the most well documented. A side benefit might be that it provides a
convenient benchmark and launching point for further implementations since
it kind of is the distilled essence of what a VAX is.
As for your points about the 68k, I think you are being a little
optimistic. 5000 LEs is a lot. For example, if I am remembering my numbers
correctly, I believe the LEON3, which is a FOSS version of the SPARCv8,
uses something like 3500, and that has all kinds of incredibly complex
stuff to deal with. Moreover, an NVAX is more akin to a 68040 in terms of
complexity. In any case, my goal here is to get something running, not
create the world's best VAX. For this to be of any use whatsoever, it would
need to fit on boards that cost no more than $150 or so. I don't think that
the LEON3 can fit on the Spartan-6 LX9 that the Papilio Pro board uses.
Anyway, this certainly warrants more research. Thanks for the links.
On 16 July 2014 15:53, Peter Corlett <abuse at cabal.org.uk> wrote:
On Wed, Jul 16, 2014 at 02:11:26PM -0600, emanuel
stiebler wrote:
--
Thanks,
Kevin
On 2014-07-16 12:04, David Riley wrote:
> Making a wild-ass guess, with careful design, you could probably run
> something at least as fast as a KA650 (CVAX) on even a cheap modern
FPGA.
> But that's a wholly uninformed guess; it
could be either way faster or
way
> slower.
It should be possible to catch up to a NVAX, but
it probably is on
really modern low cost FPGAs.
Thar Interwebs tells me that the KA650 has roughly 2.5 VUPs, with a VUP
equvalent to the bog standard 1977-vintage VAX 11/780, and further that the
11/780 ran at 5MHz and the superficial design elements seem similar to a
CPU I
am more familiar with, the 68000. The VAX has paging hardware -- the
giveaway
is in the acronym! -- which makes it a bit more complex, but we're still
in the
same sort of ballpark.
So, here's a soft 68000: https://github.com/alfikpl/ao68000
The README.md notes that it has similar IPC to the 68000, is good for up to
about 82MHz, and uses roughly 5,000 LEs and 46kb of memory. I reckon this
means
you could get four VAX cores onto the relatively low-specced Cyclone IV
that
comes on the dirt cheap DE0-Nano FPGA dev kit.
The NVAX is 80-90MHz which is pleasingly similar to the maximum speed of
that
68000 core. Did you fancy a cluster of four NVAXen that runs on a chip that
costs something like $15 in bulk and can be powered by a lemon with a
couple of
nails banged into it?
16 Jul
16 Jul
7:31 p.m.
Peter Corlett wrote:
The NVAX is 80-90MHz which is pleasingly similar to
the maximum speed of that
68000 core. Did you fancy a cluster of four NVAXen that runs on a chip that
costs something like $15 in bulk and can be powered by a lemon with a couple of
nails banged into it?
If you include the NVAX+, the top end is even a good bit faster than 90MHz.
Peace... Sridhar
17 Jul
17 Jul
5:03 a.m.
On Jul 16, 2014 4:18 PM, "Peter Corlett" <abuse at cabal.org.uk> wrote:
The NVAX is 80-90MHz which is pleasingly similar to
the maximum speed of
that
68000 core. Did you fancy a cluster of four NVAXen
that runs on a chip
that
costs something like $15 in bulk and can be powered by
a lemon with a
couple of
nails banged into it?
Yes. But 2014 FPGA technology will not provide it at that price or at that
level of power consumption. Maybe in another ten years.
Even the off-brand FPGAs that are marketed as ultra low power aren't low
enough power to run from a lemon, and those aren't anywhere near the
density or speed you're talking about. From a lemon, about all you're going
to run is a single chip micro (MSP430, PIC, AVR, ARM Cortex-M0) at only a
couple MHz max.
An NVAX is *much* more complex than a 68000. I doubt that even the new
(read: unobtanium) Xilinx "Ultrascale" FPGAs would be able to run an
NVAX-like core at 80-90 MHz. Certainly the Virtex-7 won't, and the price of
a large enough Virtex-7 for four NVAX-like cores is closer "in bulk" to
$15000. (Last fall I did some consulting at a company that was prototyping
a new processor architecture in the largest available Virtex-6, and they
had to strip it down some to get it to fit. It was less complex than the
NVAX, but had more parallelism.)
A simpler VAX design, with much less agressive cycle count reduction, is
quite feasible in a low cost FPGA (around $50), but won't have nearly the
performance of an NVAX, and still won't run from a lemon.
In terms of price/performance, simulating a VAX on an x86 is going to be
far better than an FPGA. The point to doing it in an FPGA is as an exercise
to sharpen one's hardware design skills, and for fun.
1:13 p.m.
On 7/17/2014 3:03 AM, Eric Smith wrote:
Even the off-brand FPGAs that are marketed as ultra
low power aren't low
enough power to run from a lemon, and those aren't anywhere near the
density or speed you're talking about. From a lemon, about all you're going
to run is a single chip micro (MSP430, PIC, AVR, ARM Cortex-M0) at only a
couple MHz max.
The CMOS PDP 8 may do the trick for the lemon, but don't lemons go moldy
or Dry up after a few weeks. Ben.
8:44 p.m.
On Thu, Jul 17, 2014 at 11:13 AM, ben <bfranchuk at jetnet.ab.ca> wrote:
On 7/17/2014 3:03 AM, Eric Smith wrote:
> From a lemon, about all you're going
> to run is a single chip micro (MSP430, PIC, AVR, ARM Cortex-M0) at only a
> couple MHz max.
The CMOS PDP 8 may do the trick for the lemon, but
don't lemons go moldy
or Dry up after a few weeks. Ben.
If you mean the 6100 or 6120 chips, a Silicon Labs (Energy Micro)
EFM32 ARM Cortex-M3 microcontroller can actually run a PDP-8
simulation both faster and lower power than the 6100. CMOS technology
has advanced quite a bit over the last 38 years. :-)
18 Jul
18 Jul
10:36 a.m.
On 17/07/14 1:13 PM, ben wrote:
On 7/17/2014 3:03 AM, Eric Smith wrote:
Just like one's enthusiasm for random hardware projects!
;-)
Even the off-brand FPGAs that are marketed as
ultra low power aren't low
enough power to run from a lemon, and those aren't anywhere near the
density or speed you're talking about. From a lemon, about all you're
going
to run is a single chip micro (MSP430, PIC, AVR, ARM Cortex-M0) at only a
couple MHz max.
The CMOS PDP 8 may do the trick for the lemon, but don't lemons go moldy
or Dry up after a few weeks. Ben.
11:53 a.m.
On 7/17/2014 3:03 AM, Eric Smith wrote:
Even the off-brand FPGAs that are marketed as ultra
low power aren't low
enough power to run from a lemon, and those aren't anywhere near the
density or speed you're talking about. From a lemon, about all you're
going to run is a single chip micro (MSP430, PIC, AVR, ARM Cortex-M0) at
only a couple MHz max.
Ah. That answers a question that I had about Red Dwarf Season X,
episode 3.
17 Jul
17 Jul
1:37 p.m.
I agree 100%
If you want a "high-performing" VAX, use SIMH. This project is (would be?)
only for my own education and personal edification.
On 17 July 2014 03:03, Eric Smith <spacewar at gmail.com> wrote:
On Jul 16, 2014 4:18 PM, "Peter Corlett"
<abuse at cabal.org.uk> wrote:
--
Thanks,
Kevin
The NVAX is 80-90MHz which is pleasingly similar
to the maximum speed of
that
68000 core. Did you fancy a cluster of four
NVAXen that runs on a chip
that
costs something like $15 in bulk and can be
powered by a lemon with a
couple of
nails banged into it?
Yes. But 2014 FPGA technology will not provide it at that price or at that
level of power consumption. Maybe in another ten years.
Even the off-brand FPGAs that are marketed as ultra low power aren't low
enough power to run from a lemon, and those aren't anywhere near the
density or speed you're talking about. From a lemon, about all you're going
to run is a single chip micro (MSP430, PIC, AVR, ARM Cortex-M0) at only a
couple MHz max.
An NVAX is *much* more complex than a 68000. I doubt that even the new
(read: unobtanium) Xilinx "Ultrascale" FPGAs would be able to run an
NVAX-like core at 80-90 MHz. Certainly the Virtex-7 won't, and the price of
a large enough Virtex-7 for four NVAX-like cores is closer "in bulk" to
$15000. (Last fall I did some consulting at a company that was prototyping
a new processor architecture in the largest available Virtex-6, and they
had to strip it down some to get it to fit. It was less complex than the
NVAX, but had more parallelism.)
A simpler VAX design, with much less agressive cycle count reduction, is
quite feasible in a low cost FPGA (around $50), but won't have nearly the
performance of an NVAX, and still won't run from a lemon.
In terms of price/performance, simulating a VAX on an x86 is going to be
far better than an FPGA. The point to doing it in an FPGA is as an exercise
to sharpen one's hardware design skills, and for fun.
16 Jul
16 Jul
6:24 p.m.
On 16 July 2014 12:04, David Riley <fraveydank at gmail.com> wrote
The CPU design is actually pretty cleanly divided up into boxes that
fulfill
various architectural features; I'd suggest reading the Digital Technical
Journal articles on the design and implementation of NVAX as a primer.
Funnily enough, I was actually just reading that very article! It was very
interesting and enlightening.
If you're interested in starting a project,
I'm somewhat interested in
contributing, as it's something I've had on my mind for a long time. I
don't have a lot of free time these days, but I may in the not-too-distant
future.
Unfortunately, I can't really commit to anything at the moment, but I'll be
sure and let you know if and when I can.
Thanks for all your advice
--
Thanks,
Kevin
2:14 p.m.
On 2014-07-16 11:49, Kevin Keith wrote:
Basically, my question is what are the major obstacles
(besides the breadth
of the project) to implementing the VAX in an FPGA, as compared to any
other ISA?
VAX CPU Core is actually pretty straight forward, and you will have
something running pretty fast. (If you know Verilog or VHDL already,
and not fighting a language)
And it is very well documented, so you can read up, how it really
works between the different models.
Are you bored?
;-)
Cheers
2:29 p.m.
On 7/16/2014 10:49 AM, Kevin Keith wrote:
Basically, my question is what are the major obstacles
(besides the
breadth of the project) to implementing the VAX in an FPGA, as
compared to any other ISA?
There are VAX-11/780 schematics, PLD truth tables, and microcode
available on bitsavers.org. I'd think that you could implement a '780
from the schematics.
Rob.
2:53 p.m.
On 2014-07-16 12:29, Rob Doyle wrote:
On 7/16/2014 10:49 AM, Kevin Keith wrote:
So, what did you have in mind?
To implement a specific model as close as possible to the original,
or just a fast VAX which doesn't need air conditioning?
Basically, my question is what are the major
obstacles (besides the
breadth of the project) to implementing the VAX in an FPGA, as
compared to any other ISA?
There are VAX-11/780 schematics, PLD truth tables, and microcode
available on bitsavers.org. I'd think that you could implement a '780
from the schematics. 
3:28 p.m.
Tokai University did this a few years ago with the 11/780.
Zane
On Jul 16, 2014, at 10:49 AM, Kevin Keith <krfkeith
at gmail.com> wrote:
Basically, my question is what are the major obstacles (besides the breadth
of the project) to implementing the VAX in an FPGA, as compared to any
other ISA?
3:51 p.m.
I think a major issue is that as Vaxen are readily (well I have two Vax
Stations so they can't me that uncommon) available, then there isn't the
same incentive as for other platforms. I also think that it would be
advantageous to have some kind of BUS implementation. One of the great
things about the VAX is the expansion bus....
Dave
G4UGM
-----Original Message-----
From: cctalk-bounces at classiccmp.org [mailto:cctalk-bounces at classiccmp.org]
On Behalf Of Zane H. Healy
Sent: 16 July 2014 20:28
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: Yet Another FPGA VAX Discussion
Tokai University did this a few years ago with the 11/780.
Zane
On Jul 16, 2014, at 10:49 AM, Kevin Keith <krfkeith
at gmail.com> wrote:
Basically, my question is what are the major obstacles (besides the
breadth of the project) to implementing the VAX in an FPGA, as
compared to any other ISA
4:32 p.m.
Sorry Eric, I meant to say "busses" as the VaxStations I have only have SCSI,
the MicroVaxes I used at work were, I think QBUS, and I believe the 11/750 (and 780?) had
Unibus I believe....
Dave
-----Original Message-----
From: cctalk-bounces at classiccmp.org [mailto:cctalk-bounces at classiccmp.org] On Behalf
Of Eric Smith
Sent: 16 July 2014 21:11
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: Yet Another FPGA VAX Discussion
On Wed, Jul 16, 2014 at 1:51 PM, Dave G4UGM <dave.g4ugm at gmail.com> wrote:
One of the great
things about the VAX is the expansion bus....
With VAXen, there isn't any "the" expansion bus.
5:07 p.m.
Dave G4UGM wrote:
Sorry Eric, I meant to say "busses" as the
VaxStations I have only
have SCSI, the MicroVaxes I used at work were, I think QBUS, and I
believe the 11/750 (and 780?) had Unibus I believe....
At least:
Qbus
Unibus
VAXBI
XMI
Laserbus
SCSI
DSSI
CI
SDI
ST506
Some of them are more "necessary" than others, obviously.
Peace... Sridhar
5:33 p.m.
On Jul 16, 2014, at 5:07 PM, Sridhar Ayengar <ploopster at gmail.com> wrote:
Dave G4UGM wrote:
Also Futurebus. Or did that never make it out the door? I remember a pile of work on
that. Very strange bus, not well named. :-)
paul
Sorry Eric, I meant to say "busses" as
the VaxStations I have only
have SCSI, the MicroVaxes I used at work were, I think QBUS, and I
believe the 11/750 (and 780?) had Unibus I believe....
At least:
Qbus
Unibus
VAXBI
XMI
Laserbus
SCSI
DSSI
CI
SDI
ST506
Some of them are more "necessary" than others, obviously.
Peace... Sridhar 
17 Jul
17 Jul
12:10 a.m.
On Wed, Jul 16, 2014 at 6:21 PM, David Riley <fraveydank at gmail.com> wrote:
On Jul 16, 2014, at 5:33 PM, Paul Koning wrote:
The Futurebus+ isn't what it used to be.
(I even have one... in a chest-high Alpha box)
-ethan
Also Futurebus. Or did that never make it out
the door? I remember a pile of work on that. Very strange bus, not well named. :-)
Depends on your definition of "well named". It was a
great name, it just wasn't accurate. :-) 
16 Jul
16 Jul
6:51 p.m.
On 16/07/14 22:33, Paul Koning wrote:
Also Futurebus. Or did that never make it out the
door? I remember a
pile of work on that. Very strange bus, not well named. :-) paul
The DEC Alpha "Cobra" (DEC 4000-6xx iirc) used that didn't it?
DECnis did too.
There was a published standard for it. (Although I may be confusing FB
and FB+ ...)
Antonio
4:12 p.m.
On Jul 16, 2014, at 3:51 PM, Dave G4UGM <dave.g4ugm at gmail.com> wrote:
I think a major issue is that as Vaxen are readily
(well I have two Vax
Stations so they can't me that uncommon) available, then there isn't the
same incentive as for other platforms. I also think that it would be
advantageous to have some kind of BUS implementation. One of the great
things about the VAX is the expansion bus....
Which one? Off the top of my head, I can think of:
- QBUS (easily emulated, but bus levels are a pain)
- Unibus (same)
- VAXBI (super-proprietary with little known documentation)
- XBI (I don't even know)
- SBI (is that even separate from VAXBI?)
If I were to make an FPGA implementation, I think I'd probably start
with an SoC of sorts, then add external bus addressing once hardware
was made. I already have it in mind to make a QBUS interface card,
but again, the round tuits are getting scarce around here these days.
- Dave
4:46 p.m.
David Riley wrote:
On Jul 16, 2014, at 3:51 PM, Dave G4UGM <dave.g4ugm
at gmail.com> wrote:
- Laserbus
Peace... Sridhar
I think a major issue is that as Vaxen are
readily (well I have two Vax
Stations so they can't me that uncommon) available, then there isn't the
same incentive as for other platforms. I also think that it would be
advantageous to have some kind of BUS implementation. One of the great
things about the VAX is the expansion bus....
Which one? Off the top of my head, I can think of:
- QBUS (easily emulated, but bus levels are a pain)
- Unibus (same)
- VAXBI (super-proprietary with little known documentation)
- XBI (I don't even know)
- SBI (is that even separate from VAXBI?)
9:59 p.m.
there is a link on my DEC emulation site in the fpga section, but I think it's dead.
In the air, and connection sucks.
Zane
On Jul 16, 2014, at 3:29 PM, Kevin Keith <krfkeith
at gmail.com> wrote:
On 16 July 2014 13:28, Zane H. Healy <healyzh at aracnet.com> wrote:
Tokai University did this a few years ago with the 11/780.
I've seen references to this, but never any actual code, do you have a
link?
17 Jul
17 Jul
12:53 a.m.
I could have sworn that there had been code on their website, but based on archive.org, it
looks like they never got it posted, the website appears to have stopped being updated
about the time the were starting work on the VAX design.
Zane
On Jul 16, 2014, at 6:59 PM, Zane Healy <healyzh at aracnet.com> wrote:
there is a link on my DEC emulation site in the fpga
section, but I think it's dead. In the air, and connection sucks.
Zane
On Jul 16, 2014, at 3:29 PM, Kevin Keith
<krfkeith at gmail.com> wrote:
On 16 July 2014 13:28, Zane H. Healy <healyzh at aracnet.com> wrote:
Tokai University did this a few years ago with the 11/780.
I've seen references to this, but never any actual code, do you have a
link?
12:58 a.m.
Yeah. . .sadly, I came to the same conclusion as well :/
On Jul 16, 2014 10:57 PM, "Zane Healy" <healyzh at aracnet.com> wrote:
I could have sworn that there had been code on their
website, but based on
archive.org, it looks like they never got it posted, the website appears
to have stopped being updated about the time the were starting work on the
VAX design.
Zane
On Jul 16, 2014, at 6:59 PM, Zane Healy <healyzh at aracnet.com> wrote:
there is a link on my DEC emulation site in the
fpga section, but I
think it's dead. In the air, and connection sucks.
Zane
On Jul 16, 2014, at 3:29 PM, Kevin Keith
<krfkeith at gmail.com> wrote:
On 16 July 2014 13:28, Zane H. Healy <healyzh at aracnet.com> wrote:
Tokai University did this a few years ago with the 11/780.
I've seen references to this, but never any actual code, do you have a
link?
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