The NVAX is an *amazingly* well done design. IIRC, it even has a limited
form of Out-of-order execution similar to the CDC 6600. Nevertheless, it
also was very complicated and is definitely beyond the scope of this
project. There are a few open FPU cores floating around, although adapting
them to use VAX floating point format might be rather difficult.
Anyway, concerning an 11/780 reimplementation, it might be best to leave
out a few of the more complicated things. Probably the MicroVAX instruction
subset might be a good place to start. Compatibility mode, in particular,
is probably not really worthwhile to leave in.
On 16 July 2014 16:28, David Riley <fraveydank at gmail.com> wrote:
On Jul 16, 2014, at 5:53 PM, Peter Corlett wrote:
Thar Interwebs tells me that the KA650 has
roughly 2.5 VUPs, with a VUP
equvalent to the bog standard 1977-vintage VAX 11/780, and further that
the
11/780 ran at 5MHz and the superficial design
elements seem similar to a
CPU I
am more familiar with, the 68000. The VAX has
paging hardware -- the
giveaway
is in the acronym! -- which makes it a bit more
complex, but we're still
in the
same sort of ballpark.
So, here's a soft 68000:
https://github.com/alfikpl/ao68000
The README.md notes that it has similar IPC to the 68000, is good for up
to
about 82MHz, and uses roughly 5,000 LEs and 46kb
of memory. I reckon
this means
you could get four VAX cores onto the relatively
low-specced Cyclone IV
that
comes on the dirt cheap DE0-Nano FPGA dev kit.
The NVAX is 80-90MHz which is pleasingly similar to the maximum speed of
that
68000 core. Did you fancy a cluster of four
NVAXen that runs on a chip
that
costs something like $15 in bulk and can be
powered by a lemon with a
couple of
nails banged into it?
You should be able to get that frequency out of it, but I doubt
you'd get the same performance per clock that you would out of
an NVAX (at least not without committing an awful lot of area).
NVAX had some really neat, sophisticated macropipelining and
other interesting ILP features that popped up right at the end
of the CISC CPU era (x86 notwithstanding, since they did a bit
of an end run around the CISC concept).
The (original) 68000, in contrast, is actually a really simple
design based around a 16-bit ALU and a piss-poor bus interface
unit with no bursting. I imagine if you implemented the
architectural features of, say, a 68040 in an FPGA, that you'd
run up the area quite a bit even without the monstrous FPU.
Still, going back to VAX-land, I'll bet you could get something
in between an NVAX and a CVAX, performance-wise, out of a
Cyclone IV without really blowing the utilization out of the
water. I'm definitely interested in contributing to such a
project, and I do FPGA design at all levels of performance and
cost as my dayjob.
- Dave