16 Nov
2011
16 Nov
'11
8:50 p.m.
On 11/16/2011 11:31 PM, Dave McGuire wrote:
On 11/16/2011 06:31 PM, Keith Monahan wrote:
In this particular case, Xilinx gives you a memory generator as part of
their CoreGen. You plug in a bunch of variables for the size of the
memory, width, depth, frequency, pipeline, burst, blah, blah and it
spits out a supposedly working memory controller.
They go so far as to say that every permutation has been verified to
ensure correctness. The result is something like 7300 lines of verilog
(or vhdl, your choice) across a bunch of directories and files.
Keith
You wouldn't happen to be talking about
Xilinx's memory controller,
would you? I get a ton of warnings. And it's surprising when they design
both the controller and synthesizer.
Those types of things, code in app notes and whatnot, are often thrown
to interns and "summer slaves" as busy work. Some of the worst (and
worst architecturally-"fitting") code I've ever seen has been in app
notes from the manufacturers of the chip in question. So, often, the
only link between the people who designed the controller and the people
who designed the synthesizer is the name on the top of their paycheck.
-Dave