2 Sep
2014
2 Sep
'14
7:12 p.m.
And here's the next question.. it's about this PROT/UNPROT feature.. it's a
write-protect feature for the system RAM.
As noted earlier, all the control panel does is supply buffered signals
from the toggle switch to the mainboard, which must be
supported &
acknowledged by the memory board.
I don't see any connections to the relevant pins, on either the SD Systems
(DRAM) board or the CCS (SRAM) board, that would support this feature. So
the question is, is the memory protection feature some sort of proprietary
MITS / Altair feature that just wasn't picked up by 3rd party mfr's?
Would I expect to see protection implemented on the genuine MITS memory
boards - and not on 3rd party? Because it does seem that it's all up to the
board design as to whether or not this is supported. Come to think, I need
to look at the docs for the MITS 1K / 4K boards.
On Tue, Sep 2, 2014 at 8:15 PM, drlegendre . <drlegendre at gmail.com> wrote:
Brent & All,
A big thanks to you, Brent.. you were a great help.
But yeah, the switch positions are essentially backwards from the
indications in the doc. I was able to sort that, but it's still kind of a
creepy feeling.. I sympathize for the (person like myself) 40 years ago
without any kind of experienced support & assistance on-tap. I've written
kit assembly & owners manuals for stuff that's more complex to build than
that board, and even I managed to get my ons and offs coherent and easily
understood!
I'm sure it's small potatoes for folks like yourself, but for me, this is
a big breakthrough.. some confirmatory evidence of my progress up the
learning curve. A couple more rounds like this, and I'll need some bigger
fish to fry.. then lookout, lol!
(Oh, and after reading about two dozen datasheets for 74XX I +do+ know how
TTL stuff is built, internally. Ain't nothing but xistors, diodes,
resistors and caps in there, for the most part. It could all be built from
basic discrete components - and more importantly, it once +was+. It's all
about the "I" in "IC", eh?)
On Tue, Sep 2, 2014 at 7:49 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Sep-02, at 3:12 PM, drlegendre . wrote:
So then, let's move on to the section on
configuring the switches on the
board. Frankly, it appears not only confusing and just plain wrong, it
also
appears to contradict itself. I think this is the
stuff that Brent was
mentioning earlier - if you set those switches the way the doc
indicates,
the memory gets mapped to the top-end of the 64K
range, as opposed to
the
bottom end. That one I verified. Also, the
switches on the board are in
reverse order vs. the switch tables drawn in the manual
It's confusing because:
- there's half-a-dozen levels of inversion going on in the circuitry,
- they installed some switches with the opposite open/closed
orientation to that of the design,
- and the off/on in the doc refers to the bit values, not the switch
positions.
I think the four address-group switch-sets for your board should be:
UUDD DUDD UDDD DDDD
U = up, towards top edge of board
D = down, towards edge connector
The other small switch-set WA/BO/BD looks opposite to the doc too.
Then there's the strange statement..
"closed=0 open=1", bottom of p.1-5.
Now that defies every convention known to man.. 0=false=open=off /
1=true=closed=on in my world.
Sometimes the convention used in some field of study (boolean logic)
doesn't match up with a physical implementation (TTL electronics).
Closing the switch pulls the line low, to GND. This is standard with TTL
because TTL is in an implementation class of logic called current-sinking
logic (look up a resource that shows how TTL works electrically).
It's much more power-efficient to do it this way than the reverse. Also,
sometimes it's preferable to have one side of a switch at GND rather than
+V.
Whether that closed switch is going to match or complement the '1' in an
address bit depends on how many inversions occur in the address comparison
circuitry.
Anyways .. Yay! - a functioning Altair.