30 Aug
2014
30 Aug
'14
10:17 a.m.
I've been trying to familiarize myself with the soon-to-arrive SRAM board,
reading through the documentation, googling this & that, etc. But I'm
having trouble understanding a couple of concepts..
(You can d/l the manual for the board at http://nerp.net/~legendre/altair/
- "California Computer Systems 2016B". There's a pic there as well.)
I get that the S-100 memory space is organized into 16 blocks of 4096
(8-bit) bytes, with the high-order digit in the memory address denoting the
block number (0XXX-FXXX). This would correspond to address lines A12-A15.
Likewise, I get that the SRAM board is organized into 4 blocks of 4096
bytes per block, and that with the corresponding DIP switches, I can
individually map each 4K block into any of the 16 blocks in the memory
space. Great, I know how to configure the memory blocks..
But now what is this about 'banks'?
On p.33, section 3.3 the manual states "The 2016B is bank-selectable by
bank port address and bank byte. Thus it is fully compatible with Cromemco,
Alpha Micro and other port-bank-select systems. IT IS NOT COMPATIBLE WITH
ADDRESS-SELECT SYSTEMS SUCH AS IMSAI."
So what does that mean to me? There are apparently two parameters, Bank
Byte and Bank Port Address - and I just can't get what they're about. How
does a bank differ from a block, and why do I need to configure those
settings? And is this card even compatible with the Altair - I don't know
if it uses the former or latter (IMSAI) scheme..
As ever, thanks for your help!
30 Aug
30 Aug
12:49 p.m.
On 2014-Aug-30, at 10:17 AM, drlegendre . wrote:
I've been trying to familiarize myself with the
soon-to-arrive SRAM board,
reading through the documentation, googling this & that, etc. But I'm
having trouble understanding a couple of concepts..
(You can d/l the manual for the board at http://nerp.net/~legendre/altair/
- "California Computer Systems 2016B". There's a pic there as well.)
I get that the S-100 memory space is organized into 16 blocks of 4096
(8-bit) bytes, with the high-order digit in the memory address denoting the
block number (0XXX-FXXX). This would correspond to address lines A12-A15.
Likewise, I get that the SRAM board is organized into 4 blocks of 4096
bytes per block, and that with the corresponding DIP switches, I can
individually map each 4K block into any of the 16 blocks in the memory
space. Great, I know how to configure the memory blocks..
But now what is this about 'banks'?
On p.33, section 3.3 the manual states "The 2016B is bank-selectable by
bank port address and bank byte. Thus it is fully compatible with Cromemco,
Alpha Micro and other port-bank-select systems. IT IS NOT COMPATIBLE WITH
ADDRESS-SELECT SYSTEMS SUCH AS IMSAI."
So what does that mean to me? There are apparently two parameters, Bank
Byte and Bank Port Address - and I just can't get what they're about. How
does a bank differ from a block, and why do I need to configure those
settings? And is this card even compatible with the Altair - I don't know
if it uses the former or latter (IMSAI) scheme..
As ever, thanks for your help!
Earlier in the thread:
"In addition to the typical address-range enable, S100 memory boards could commonly
have two additional enabling schemes:
- Bank enable/disable - allowed memory sizes greater than 64K by allowing memory
boards to be enabled/disabled by writing to a dedicated I/O port.
Your board/bank needs to be enabled as bank 0 or bank operation disabled.
- Phantom disable - allowed a memory board to be disabled at reset and later enabled
under program control,
to allow initial overlaying by boot ROMs.
The phantom function should be disabled (the board should ignore phantom, so its
always enabled)
"
Confusion can arise from the ambiguity of the word "bank". In S100 systems
"bank" refers to the facility to have turn on and off multiple 64K address
spaces in the system. The CCS manual refers to the 4K blocks on the memory board as
"groups", these are 4K ranges within one 64K address space, distinct from the
multiple-64K-address-space "banks". (Note that the 4K 'groups'
aren't anything to do with S100, it's just an organizational characteristic of
that board.)
You need to disable the bank facility for the board:
Sec 1.4. To make the 2016B bank-independant, .. close the BD switch.
With that done, the bank address and bank byte switches shouldn't matter.
Nothing else in the system should be asserting phantom so it shouldn't matter whether
the phantom jumper is installed, but you could remove it to be sure. (Sec 1.7)
The schematic scan in the pdf is pretty horrible, but if I'm reading it right, upon
power-up the BANK LED should be lit. The BOARD LED should light when the board is
addressed.
Going from what I'm seeing you may have to be careful to note the open/closed
orientation of the switches, as it appears the installed switches aren't always
consistent with the config diagrams in the manual.
I actually have the JTS version of that board (same board marketed under a different
name).
1:36 p.m.
On Sat, Aug 30, 2014 at 2:49 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
Earlier in the thread:
Really, where? In this thread? Hmm.. don't see it.
"In addition to the typical
address-range enable, S100
memory boards could commonly have two additional enabling schemes:
- Bank enable/disable - allowed memory sizes
greater than 64K by allowing memory boards to be enabled/disabled by
writing to a dedicated I/O port.
Your board/bank needs to be enabled as bank 0 or
bank operation disabled.
- Phantom disable - allowed a memory board to be
disabled at reset and later enabled under program control,
to allow initial overlaying by boot ROMs.
The phantom function should be disabled (the
board should ignore phantom, so its always enabled)
Yep, I've got it now. It's exactly the same situation as in the C-64, which
I'm much more familiar with. The C-64 also has a 16-bit address buss, hence
a 64K memory space. It also has 64K of RAM and around 24K of on-board ROM
with an expansion port for more. So when BASIC is up & running, it
banks-out 24K of RAM and banks-in 3x 8K ROMs - BASIC, kernal and chargen.
This leaves 40K of RAM in the memory space, but the system grabs around 2K
of that for overhead, leaving around 38K for the user.
By changing the value of a register on zero-page (IIRC) you can configure
several different memory maps, with varying amounts of RAM / ROM occupying
various ranges in the space. It's not quite as versatile as the system here
discussed, but it's still the same basic concept serving the same basic
purposes in both systems.
Nothing else in the system should be asserting phantom so it shouldn't
matter whether the phantom jumper is installed, but you could remove it to
be sure. (Sec 1.7)
I was wondering about Phantom.. as yes, it does seem to duplicate the same
functions as banking. But it seems that Phantom is only used upon reset, or
power-up, to +temporarily+ overlay boot code which then "disappears" for
the remainder of the session once it's served its purpose and the phantom
line is released.
So then, asserting Phantom when the system is operating has no effect -
correct? It only acts after a reset event? It would be like the action of a
J-K lfip-flop - the J/K lines cannot change the state of Q on their own,
they only determine what value Q will take on the rising-edge of the next
clock cycle (the reset event, for phantom).
Do I have that right?
Going from what I'm seeing you may have to be
careful to note the
open/closed orientation of the switches, as it appears the installed
switches aren't always consistent with the config diagrams in the manual.
Yes, duly noted.. I saw that.
I actually have the JTS version of that board (same board marketed under a
different name).
The board I'm receiving is marked JTS on the rear.. so I guess we've got
the same one!
6:04 p.m.
On 2014-Aug-30, at 1:36 PM, drlegendre . wrote:
Message from me of 2014 August 27 1:45:56 PM PDT.
Generally speaking yes. On system reset, some flip-flop on a PROM board would be set,
enabling the PROM and asserting phantom on the bus, to disable a RAM board so the PROM can
overlay it. Some subsequent action during boot would trigger the PROM board flip-flop off
and de-assert phantom so you now had full RAM available.
But the RAM boards are passive responders to the phantom signal, there's nothing
prohibiting a system design or PROM board design from reasserting phantom at a later time
under some program action.
Correcting myself .. JTM.
If that photo on your site is the actual instance which you are to receive then yes, they
look quite the same.
Except the 5 CTS switch blocks on the photo instance have reversed on/off positions to the
one I have (and from the manual).
I was just playing with the one here to get it working.
On Sat, Aug 30, 2014 at 2:49 PM, Brent Hilpert
<hilpert at cs.ubc.ca> wrote:
Earlier in the
thread:
Really, where? In this thread? Hmm.. don't see it. Nothing else
in the system should be asserting phantom so it shouldn't
matter whether the phantom jumper is installed, but you could remove it to
be sure. (Sec 1.7)
I was wondering about Phantom.. as yes, it does seem to duplicate the same
functions as banking. But it seems that Phantom is only used upon reset, or
power-up, to +temporarily+ overlay boot code which then "disappears" for
the remainder of the session once it's served its purpose and the phantom
line is released.
So then, asserting Phantom when the system is operating has no effect -
correct? It only acts after a reset event? It would be like the action of a
J-K lfip-flop - the J/K lines cannot change the state of Q on their own,
they only determine what value Q will take on the rising-edge of the next
clock cycle (the reset event, for phantom).
Do I have that right? > Going from what I'm seeing you may have to be
careful to note the
> open/closed orientation of the switches, as it appears the installed
> switches aren't always consistent with the config diagrams in the manual.
Yes, duly noted.. I saw that.
> I actually have the JTS version of that board
(same board marketed under a
> different name).
The board
I'm receiving is marked JTS on the rear.. so I guess we've got
the same
one!
7:37 p.m.
Yes, 'JTM' is in fact correct - that's what the seller stated in the
listing. I was just following your lead, and didn't notice the typo.
And again, per the seller, that photo on my ~legendre site is supposedly
the selfsame board which I am receiving. Looks to be in very nice cosmetic
shape, hopefully it didn't suffer electronically at some point.
On Sat, Aug 30, 2014 at 8:04 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Aug-30, at 1:36 PM, drlegendre . wrote:
Message from me of 2014 August 27 1:45:56 PM PDT.
same
Correcting myself .. JTM.
If that photo on your site is the actual instance which you are to receive
then yes, they look quite the same.
Except the 5 CTS switch blocks on the photo instance have reversed on/off
positions to the one I have (and from the manual).
I was just playing with the one here to get it working.
On Sat, Aug 30, 2014 at 2:49 PM, Brent Hilpert
<hilpert at cs.ubc.ca>
wrote:
Earlier
in the thread:
Really, where? In this thread? Hmm.. don't see it. > Nothing else in the system should be
asserting phantom so it shouldn't
> matter whether the phantom jumper is installed, but you could remove
it to
be sure.
(Sec 1.7)
I was wondering about Phantom.. as yes, it does seem to duplicate the functions as banking. But it seems that Phantom
is only used upon reset,
or
power-up, to +temporarily+ overlay boot code
which then "disappears" for
the remainder of the session once it's served its purpose and the phantom
line is released.
So then, asserting Phantom when the system is operating has no effect -
correct? It only acts after a reset event? It would be like the action
of a
J-K lfip-flop - the J/K lines cannot change the
state of Q on their own,
they only determine what value Q will take on the rising-edge of the next
clock cycle (the reset event, for phantom).
Do I have that right?
Generally speaking yes. On system reset, some flip-flop on a PROM board
would be set, enabling the PROM and asserting phantom on the bus, to
disable a RAM board so the PROM can overlay it. Some subsequent action
during boot would trigger the PROM board flip-flop off and de-assert
phantom so you now had full RAM available.
But the RAM boards are passive responders to the phantom signal, there's
nothing prohibiting a system design or PROM board design from reasserting
phantom at a later time under some program action.
> Going from what I'm seeing you may have
to be careful to note the
> open/closed orientation of the switches, as it appears the installed
> switches aren't always consistent with the config diagrams in the
manual.
Yes, duly noted.. I saw that.
> I actually have the JTS version of that board
(same board marketed
under a
> different name).
The board
I'm receiving is marked JTS on the rear.. so I guess we've got
the same
one!
31 Aug
31 Aug
10:48 a.m.
Couple of questions have come up..
While waiting for the new SRAM card to arrive, I thought I'd see what I
could learn about the SD Systems 'Expandoram II' DRAM card I currently
have. One major difference that I immediately noticed is the lack of a
block-address assignment feature. The JTM board allows the user to
arbitrarily map each of the (4) 4K groups to any 4K boundary in the memory
space. But the SD card is organized into 4x 16K groups, and each group can
only be enabled or disabled.
Oddly, I can't find any info on the mapping scheme in the document. For
example, if only group 3 is enabled, where does it map? 0000-4000 or
C000-FFFF.. or elsewhere?
But here's my +real+ question.. the document has a section on operating the
board in non-SD Systems environments, and that would seem to apply, here.
They state that "Some CPU boards (they don't mention which) supply a
different phase of the system clock on pins 24 & 25. If one of these boards
is used with the Expandoram II, make the following changes...", and then go
on to describe the changes - basic cut & jumper stuff, two locations.
Does anyone know if this difference in clock signals is relevant to the
MITS 8080 CPU board? If the board isn't receiving the clock it expects,
it's no surprise that it seems to behave so badly, eh..? Perhaps just go
ahead and make the changes and give it a go? It's easy enough to revert it,
if it doesn't help.
Lastly, I also discovered that the SD board had Wait State enabled.. and
the doc says that's only required for 4MHz CPU operation. The 8080A runs at
2Mhz, so I've disabled the wait state. Not sure if that was screwing things
up as well, but +probably+ not - it would just slow down the RAM access,
wouldn't it? Phantom was also enabled, and it's certainly not needed in
this instance, so I disabled that as well.
Any ideas on the mapping issue? Or more importantly, the clocking issue?
On Sat, Aug 30, 2014 at 9:37 PM, drlegendre . <drlegendre at gmail.com> wrote:
Yes, 'JTM' is in fact correct - that's
what the seller stated in the
listing. I was just following your lead, and didn't notice the typo.
And again, per the seller, that photo on my ~legendre site is supposedly
the selfsame board which I am receiving. Looks to be in very nice cosmetic
shape, hopefully it didn't suffer electronically at some point.
On Sat, Aug 30, 2014 at 8:04 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Aug-30, at 1:36 PM, drlegendre . wrote:
Message from me of 2014 August 27 1:45:56 PM PDT.
same
On Sat, Aug 30, 2014 at 2:49 PM, Brent Hilpert
<hilpert at cs.ubc.ca>
wrote:
Earlier
in the thread:
Really, where? In this thread? Hmm.. don't see it. > Nothing else in the system should be
asserting phantom so it
shouldn't
> matter whether the phantom jumper is
installed, but you could remove
it to
be sure.
(Sec 1.7)
I was wondering about Phantom.. as yes, it does seem to duplicate the functions as banking. But it seems that Phantom
is only used upon
reset, or
power-up, to +temporarily+ overlay boot code
which then "disappears" for
the remainder of the session once it's served its purpose and the
phantom
line is released.
So then, asserting Phantom when the system is operating has no effect -
correct? It only acts after a reset event? It would be like the action
of a
J-K lfip-flop - the J/K lines cannot change the
state of Q on their own,
they only determine what value Q will take on the rising-edge of the
next
clock cycle (the reset event, for phantom).
Do I have that right?
Generally speaking yes. On system reset, some flip-flop on a PROM board
would be set, enabling the PROM and asserting phantom on the bus, to
disable a RAM board so the PROM can overlay it. Some subsequent action
during boot would trigger the PROM board flip-flop off and de-assert
phantom so you now had full RAM available.
But the RAM boards are passive responders to the phantom signal, there's
nothing prohibiting a system design or PROM board design from reasserting
phantom at a later time under some program action.
> Going from what I'm seeing you may have
to be careful to note the
> open/closed orientation of the switches, as it appears the installed
> switches aren't always consistent with the config diagrams in the
manual.
Yes, duly noted.. I saw that.
> I actually have the JTS version of that board
(same board marketed
under a
> different name).
> The board I'm receiving is marked JTS on
the rear.. so I guess we've
got
the same one!
Correcting myself .. JTM.
If that photo on your site is the actual instance which you are to
receive then yes, they look quite the same.
Except the 5 CTS switch blocks on the photo instance have reversed on/off
positions to the one I have (and from the manual).
I was just playing with the one here to get it working.
10:50 a.m.
Oops, forgot to mention - again, all docs including those for the SD
Systems DRAM card are available at http://nerp.net/~legendre/altair/ =)
On Sun, Aug 31, 2014 at 12:48 PM, drlegendre . <drlegendre at gmail.com> wrote:
Couple of questions have come up..
While waiting for the new SRAM card to arrive, I thought I'd see what I
could learn about the SD Systems 'Expandoram II' DRAM card I currently
have. One major difference that I immediately noticed is the lack of a
block-address assignment feature. The JTM board allows the user to
arbitrarily map each of the (4) 4K groups to any 4K boundary in the memory
space. But the SD card is organized into 4x 16K groups, and each group can
only be enabled or disabled.
Oddly, I can't find any info on the mapping scheme in the document. For
example, if only group 3 is enabled, where does it map? 0000-4000 or
C000-FFFF.. or elsewhere?
But here's my +real+ question.. the document has a section on operating
the board in non-SD Systems environments, and that would seem to apply,
here. They state that "Some CPU boards (they don't mention which) supply a
different phase of the system clock on pins 24 & 25. If one of these boards
is used with the Expandoram II, make the following changes...", and then go
on to describe the changes - basic cut & jumper stuff, two locations.
Does anyone know if this difference in clock signals is relevant to the
MITS 8080 CPU board? If the board isn't receiving the clock it expects,
it's no surprise that it seems to behave so badly, eh..? Perhaps just go
ahead and make the changes and give it a go? It's easy enough to revert it,
if it doesn't help.
Lastly, I also discovered that the SD board had Wait State enabled.. and
the doc says that's only required for 4MHz CPU operation. The 8080A runs at
2Mhz, so I've disabled the wait state. Not sure if that was screwing things
up as well, but +probably+ not - it would just slow down the RAM access,
wouldn't it? Phantom was also enabled, and it's certainly not needed in
this instance, so I disabled that as well.
Any ideas on the mapping issue? Or more importantly, the clocking issue?
On Sat, Aug 30, 2014 at 9:37 PM, drlegendre . <drlegendre at gmail.com>
wrote:
Yes, 'JTM' is in fact correct -
that's what the seller stated in the
listing. I was just following your lead, and didn't notice the typo.
And again, per the seller, that photo on my ~legendre site is supposedly
the selfsame board which I am receiving. Looks to be in very nice cosmetic
shape, hopefully it didn't suffer electronically at some point.
On Sat, Aug 30, 2014 at 8:04 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Aug-30, at 1:36 PM, drlegendre . wrote:
On Sat, Aug 30, 2014 at 2:49 PM, Brent Hilpert
<hilpert at cs.ubc.ca>
wrote:
> Earlier in the thread:
Really, where? In this thread? Hmm.. don't see it.
Message from me of 2014 August 27 1:45:56 PM PDT.
> Nothing else in the system should be
asserting phantom so it
shouldn't
> matter whether the phantom jumper is
installed, but you could remove
it to
> be sure. (Sec 1.7)
I was wondering about Phantom.. as yes, it does seem to duplicate the
same
functions as banking. But it seems that Phantom
is only used upon
reset, or
power-up, to +temporarily+ overlay boot code
which then "disappears"
for
the remainder of the session once it's served
its purpose and the
phantom
line is released.
So then, asserting Phantom when the system is operating has no effect -
correct? It only acts after a reset event? It would be like the action
of a
J-K lfip-flop - the J/K lines cannot change the
state of Q on their
own,
they only determine what value Q will take on the
rising-edge of the
next
clock cycle (the reset event, for phantom).
Do I have that right?
Generally speaking yes. On system reset, some flip-flop on a PROM board
would be set, enabling the PROM and asserting phantom on the bus, to
disable a RAM board so the PROM can overlay it. Some subsequent action
during boot would trigger the PROM board flip-flop off and de-assert
phantom so you now had full RAM available.
But the RAM boards are passive responders to the phantom signal, there's
nothing prohibiting a system design or PROM board design from reasserting
phantom at a later time under some program action.
> Going from what I'm seeing you may have
to be careful to note the
> open/closed orientation of the switches, as it appears the installed
> switches aren't always consistent with the config diagrams in the
manual.
Yes, duly noted.. I saw that.
> I actually have the JTS version of that board
(same board marketed
under a
> different name).
> The board I'm receiving is marked JTS on
the rear.. so I guess we've
got
the same one!
Correcting myself .. JTM.
If that photo on your site is the actual instance which you are to
receive then yes, they look quite the same.
Except the 5 CTS switch blocks on the photo instance have reversed
on/off positions to the one I have (and from the manual).
I was just playing with the one here to get it working.
3:58 p.m.
Quick update - I made the changes described under "use in non-SD Systems
environments", to no obvious effect. I still cannot deposit / examine any
memory locations.
But one thing I did notice, I'm getting the sense that the front panel is
no longer a (significant) issue. It really does seem to behave in a sane
and predictable way, despite the fact that the rest of the hardware doesn't
play along. Some strong hints of a sane mind down in there somewhere.. it's
starting to look encouraging.
I'll use some more 'wait time' to see about improving and finalizing the
grounding & power schemes, maybe actually fasten down the mainboard.. It's
all kind of flying in the breeze at the moment..
On Sun, Aug 31, 2014 at 12:50 PM, drlegendre . <drlegendre at gmail.com> wrote:
Oops, forgot to mention - again, all docs including
those for the SD
Systems DRAM card are available at http://nerp.net/~legendre/altair/ =)
On Sun, Aug 31, 2014 at 12:48 PM, drlegendre . <drlegendre at gmail.com>
wrote:
Couple of questions have come up..
While waiting for the new SRAM card to arrive, I thought I'd see what I
could learn about the SD Systems 'Expandoram II' DRAM card I currently
have. One major difference that I immediately noticed is the lack of a
block-address assignment feature. The JTM board allows the user to
arbitrarily map each of the (4) 4K groups to any 4K boundary in the memory
space. But the SD card is organized into 4x 16K groups, and each group can
only be enabled or disabled.
Oddly, I can't find any info on the mapping scheme in the document. For
example, if only group 3 is enabled, where does it map? 0000-4000 or
C000-FFFF.. or elsewhere?
But here's my +real+ question.. the document has a section on operating
the board in non-SD Systems environments, and that would seem to apply,
here. They state that "Some CPU boards (they don't mention which) supply a
different phase of the system clock on pins 24 & 25. If one of these boards
is used with the Expandoram II, make the following changes...", and then go
on to describe the changes - basic cut & jumper stuff, two locations.
Does anyone know if this difference in clock signals is relevant to the
MITS 8080 CPU board? If the board isn't receiving the clock it expects,
it's no surprise that it seems to behave so badly, eh..? Perhaps just go
ahead and make the changes and give it a go? It's easy enough to revert it,
if it doesn't help.
Lastly, I also discovered that the SD board had Wait State enabled.. and
the doc says that's only required for 4MHz CPU operation. The 8080A runs at
2Mhz, so I've disabled the wait state. Not sure if that was screwing things
up as well, but +probably+ not - it would just slow down the RAM access,
wouldn't it? Phantom was also enabled, and it's certainly not needed in
this instance, so I disabled that as well.
Any ideas on the mapping issue? Or more importantly, the clocking issue?
On Sat, Aug 30, 2014 at 9:37 PM, drlegendre . <drlegendre at gmail.com>
wrote:
Yes, 'JTM' is in fact correct -
that's what the seller stated in the
listing. I was just following your lead, and didn't notice the typo.
And again, per the seller, that photo on my ~legendre site is supposedly
the selfsame board which I am receiving. Looks to be in very nice cosmetic
shape, hopefully it didn't suffer electronically at some point.
On Sat, Aug 30, 2014 at 8:04 PM, Brent Hilpert <hilpert at cs.ubc.ca>
wrote:
On 2014-Aug-30, at 1:36 PM, drlegendre . wrote:
> On Sat, Aug 30, 2014 at 2:49 PM, Brent Hilpert <hilpert at cs.ubc.ca>
wrote:
>> Earlier in the thread:
> Really, where? In this thread? Hmm.. don't see it.
Message from me of 2014 August 27 1:45:56 PM PDT.
> > Nothing else in the system should be asserting phantom so it
shouldn't
> > matter whether the phantom jumper is installed, but you could
remove it to
> > be sure. (Sec 1.7)
>
> I was wondering about Phantom.. as yes, it does seem to duplicate the
same
> functions as banking. But it seems that Phantom is only used upon
reset, or
> power-up, to +temporarily+ overlay boot code which then "disappears"
for
> the remainder of the session once it's served its purpose and the
phantom
> line is released.
>
> So then, asserting Phantom when the system is operating has no effect
-
> correct? It only acts after a reset event? It would be like the
action of a
> J-K lfip-flop - the J/K lines cannot change the state of Q on their
own,
> they only determine what value Q will take on the rising-edge of the
next
> clock cycle (the reset event, for phantom).
>
> Do I have that right?
Generally speaking yes. On system reset, some flip-flop on a PROM board
would be set, enabling the PROM and asserting phantom on the bus, to
disable a RAM board so the PROM can overlay it. Some subsequent action
during boot would trigger the PROM board flip-flop off and de-assert
phantom so you now had full RAM available.
But the RAM boards are passive responders to the phantom signal,
there's nothing prohibiting a system design or PROM board design from
reasserting phantom at a later time under some program action.
>> Going from what I'm seeing you may have to be careful to note the
>> open/closed orientation of the switches, as it appears the installed
>> switches aren't always consistent with the config diagrams in the
manual.
> Yes, duly noted.. I saw that.
>> I actually have the JTS version of that board (same board marketed
under a
>> different name).
>> The board I'm receiving is marked JTS on the rear.. so I guess we've
got
> the same one!
Correcting myself .. JTM.
If that photo on your site is the actual instance which you are to
receive then yes, they look quite the same.
Except the 5 CTS switch blocks on the photo instance have reversed
on/off positions to the one I have (and from the manual).
I was just playing with the one here to get it working.
1 Sep
1 Sep
1:16 p.m.
On 2014-Aug-31, at 10:48 AM, drlegendre . wrote:
Couple of questions have come up..
While waiting for the new SRAM card to arrive, I thought I'd see what I
could learn about the SD Systems 'Expandoram II' DRAM card I currently
have. One major difference that I immediately noticed is the lack of a
block-address assignment feature. The JTM board allows the user to
arbitrarily map each of the (4) 4K groups to any 4K boundary in the memory
space. But the SD card is organized into 4x 16K groups, and each group can
only be enabled or disabled.
Oddly, I can't find any info on the mapping scheme in the document. For
example, if only group 3 is enabled, where does it map? 0000-4000 or
C000-FFFF.. or elsewhere?
But here's my +real+ question.. the document has a section on operating the
board in non-SD Systems environments, and that would seem to apply, here.
They state that "Some CPU boards (they don't mention which) supply a
different phase of the system clock on pins 24 & 25. If one of these boards
is used with the Expandoram II, make the following changes...", and then go
on to describe the changes - basic cut & jumper stuff, two locations.
Does anyone know if this difference in clock signals is relevant to the
MITS 8080 CPU board? If the board isn't receiving the clock it expects,
it's no surprise that it seems to behave so badly, eh..? Perhaps just go
ahead and make the changes and give it a go? It's easy enough to revert it,
if it doesn't help.
Lastly, I also discovered that the SD board had Wait State enabled.. and
the doc says that's only required for 4MHz CPU operation. The 8080A runs at
2Mhz, so I've disabled the wait state. Not sure if that was screwing things
up as well, but +probably+ not - it would just slow down the RAM access,
wouldn't it? Phantom was also enabled, and it's certainly not needed in
this instance, so I disabled that as well.
Any ideas on the mapping issue? Or more importantly, the clocking issue?
The mapping scheme is wrapped up in the on-board address-decoding PROM chip.
It's 'described' in a rather cryptic table near the end of the manual.
It seems they intended the board for use in their own multi-user systems and didn't
feel the need
to document it thoroughly - the manual is a bit of an after-thought, like the vague
comment about the clocking.
It uses a slightly different scheme than that previously mentioned for providing multiple
64K address spaces.
It looks like the idea was to have the upper 16 or 32K as common system memory while
the lower 48/32 was swapped per user.
SDS is also using different nomenclature:
SDS bank == group (set of chips on board)
SDS page == bank (address space)
Is your board populated with 4116 chips for 64K total or some subset of 4164s?
Also, do you know whether your board has the '32K PROM' or the '48K
PROM'?
Assuming you have 4116s, cursory examination suggests the configuration switches should
be:
1 ON - enable all 4 on-board groups (SDS banks)
2 ON "
3 ON "
4 ON "
5 ON - this board is bank (SDS page) 0, with board enabled after
reset or POC
6 ON "
7 ON "
8 ON - turn on this board
If the board 'clear' jumper is set for POC rather than RESET, it will require a
good POC signal from the Altair to enable the board.
The board takes in the REFRESH signal from the S100 bus.
This is a non-standard signal that post-dates the Altair, intended to work from the Z80
refresh facility to simplify use of DRAMs.
It's not clear why they use the signal, or whether it's actually required, as it
looks like all the refresh circuitry (address counter, etc) is on the board.
Perhaps it was just to keep the refresh synchronized with other DRAM boards.
3:09 p.m.
Hi Brent & all,
The board is loaded with 4116s for a total of 64K. It has the EX2 48K PROM
chip, and the DIP switches are currently set as you suggested (all ON) -
that's also the same setting I arrived at. I also reverted the cut & jump
changes discussed earlier, the ones related to clocking and using the board
in non-SD Systems enviros.
And yes, I too caught on to their particular use of terminology... banks
vs. pages vs. groups, etc. Did prove confusing for a few moments, though.
So then I decided to go on a fishing expedition... and hooked a single dead
74LS30, U19. That has now been replaced. I've also tested all of the
74LS00, 74LS02, 74LS10, 74LS20, 74LS14, 74LS244 and 74LS373 types, all are
fine. Then I got tired of testing chips.. I'll have to figure out the other
ones later.
Being pretty new to all this, I can tell you that reading datasheets and
devising tests for 74XX series ICs is a very good way to learn your way
around the world of digital logic - it's actually been a very helpful
series of learning exercises.. far better than listening to a lecture or
reading a textbook. Man am I glad I picked up & repaired that proto /
trainer chassis.. dang thing has really been coming in handy!
Do you have any idea who made/sold it? It's pretty similar in concept to a
Heathkit ET-3200, but way more versatile. Based on the workmanship (the
occasional lack of..) I think it was built by a student, probably as part
of a tech school course, or maybe a mail correspondence course? Either way,
it's a decent piece of equipment and it works great after going through it
- https://nerp.net/~legendre/altair/photos/proto-trainer.jpg
On Mon, Sep 1, 2014 at 3:16 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Aug-31, at 10:48 AM, drlegendre . wrote:
Couple of questions have come up..
While waiting for the new SRAM card to arrive, I thought I'd see what I
could learn about the SD Systems 'Expandoram II' DRAM card I currently
have. One major difference that I immediately noticed is the lack of a
block-address assignment feature. The JTM board allows the user to
arbitrarily map each of the (4) 4K groups to any 4K boundary in the
memory
space. But the SD card is organized into 4x 16K
groups, and each group
can
only be enabled or disabled.
Oddly, I can't find any info on the mapping scheme in the document. For
example, if only group 3 is enabled, where does it map? 0000-4000 or
C000-FFFF.. or elsewhere?
But here's my +real+ question.. the document has a section on operating
the
board in non-SD Systems environments, and that
would seem to apply, here.
They state that "Some CPU boards (they don't mention which) supply a
different phase of the system clock on pins 24 & 25. If one of these
boards
is used with the Expandoram II, make the
following changes...", and then
go
on to describe the changes - basic cut &
jumper stuff, two locations.
Does anyone know if this difference in clock signals is relevant to the
MITS 8080 CPU board? If the board isn't receiving the clock it expects,
it's no surprise that it seems to behave so badly, eh..? Perhaps just go
ahead and make the changes and give it a go? It's easy enough to revert
it,
if it doesn't help.
Lastly, I also discovered that the SD board had Wait State enabled.. and
the doc says that's only required for 4MHz CPU operation. The 8080A runs
at
2Mhz, so I've disabled the wait state. Not
sure if that was screwing
things
up as well, but +probably+ not - it would just
slow down the RAM access,
wouldn't it? Phantom was also enabled, and it's certainly not needed in
this instance, so I disabled that as well.
Any ideas on the mapping issue? Or more importantly, the clocking issue?
The mapping scheme is wrapped up in the on-board address-decoding PROM
chip.
It's 'described' in a rather cryptic table near the end of the manual.
It seems they intended the board for use in their own multi-user systems
and didn't feel the need
to document it thoroughly - the manual is a bit of an after-thought, like
the vague comment about the clocking.
It uses a slightly different scheme than that previously mentioned for
providing multiple 64K address spaces.
It looks like the idea was to have the upper 16 or 32K as common system
memory while
the lower 48/32 was swapped per user.
SDS is also using different nomenclature:
SDS bank == group (set of chips on board)
SDS page == bank (address space)
Is your board populated with 4116 chips for 64K total or some subset of
4164s?
Also, do you know whether your board has the '32K PROM' or the '48K
PROM'?
Assuming you have 4116s, cursory examination suggests the configuration
switches should be:
1 ON - enable all 4 on-board groups (SDS banks)
2 ON "
3 ON "
4 ON "
5 ON - this board is bank (SDS page) 0, with board
enabled after reset or POC
6 ON "
7 ON "
8 ON - turn on this board
If the board 'clear' jumper is set for POC rather than RESET, it will
require a good POC signal from the Altair to enable the board.
The board takes in the REFRESH signal from the S100 bus.
This is a non-standard signal that post-dates the Altair, intended to work
from the Z80 refresh facility to simplify use of DRAMs.
It's not clear why they use the signal, or whether it's actually required,
as it looks like all the refresh circuitry (address counter, etc) is on the
board.
Perhaps it was just to keep the refresh synchronized with other DRAM
boards.
4:21 p.m.
On 2014-Sep-01, at 3:09 PM, drlegendre . wrote:
Hi Brent & all,
The board is loaded with 4116s for a total of 64K. It has the EX2 48K PROM
chip, and the DIP switches are currently set as you suggested (all ON) -
that's also the same setting I arrived at. I also reverted the cut & jump
changes discussed earlier, the ones related to clocking and using the board
in non-SD Systems enviros.
And yes, I too caught on to their particular use of terminology... banks
vs. pages vs. groups, etc. Did prove confusing for a few moments, though.
So then I decided to go on a fishing expedition... and hooked a single dead
74LS30, U19. That has now been replaced. I've also tested all of the
74LS00, 74LS02, 74LS10, 74LS20, 74LS14, 74LS244 and 74LS373 types, all are
fine. Then I got tired of testing chips.. I'll have to figure out the other
ones later.
I haven't examined the schematic in enough detail to quite convince myself for sure
the board will work without the RFSH signal, but that would affect the writing/retention.
To start in on board-level debugging, one thing to check: if the board is enabled and a
valid address for the board is on the bus, then U4 pin 8 should be high.
Being pretty new to all this, I can tell you that
reading datasheets and
devising tests for 74XX series ICs is a very good way to learn your way
around the world of digital logic - it's actually been a very helpful
series of learning exercises.. far better than listening to a lecture or
reading a textbook. Man am I glad I picked up & repaired that proto /
trainer chassis.. dang thing has really been coming in handy!
Do you have any idea who made/sold it? It's pretty similar in concept to a
Heathkit ET-3200, but way more versatile. Based on the workmanship (the
occasional lack of..) I think it was built by a student, probably as part
of a tech school course, or maybe a mail correspondence course? Either way,
it's a decent piece of equipment and it works great after going through it
- https://nerp.net/~legendre/altair/photos/proto-trainer.jpg
I haven't seen that model of trainer before.
I do however, remember the first of those trainers/prototypers: the E & L Instruments
Digi-Designer.
It came out in 1972, when E&L introduced those now-ubiquitous plug-boards
(subsequently copied by others).
The Digi-Designer was featured as a construction article in Radio-Electronics in Dec 72:
http://www.epanorama.net/sff/Test_equipment/Misc/Digital%20IC%20Breadboard.…
E & L Instruments is now Global Specialties it appears.
5:28 p.m.
Thanks for the input again..
On Mon, Sep 1, 2014 at 6:21 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
I haven't examined the schematic in enough detail to quite convince myself
for sure the board will work without the RFSH signal, but that would affect
the writing/retention.
I'm a bit confused.. all DRAMs need a refresh, and the doc for this board
is pretty explicit that it needs "the correct" (ugh!) phase of the clock
signal "on pins 24 & 25". Why would you think the board doesn't require
such a signal, that it has its own on-board refresh hardware? FWIW, there's
no crystal on-board to control an osc. to that level of precision.
To start in on board-level debugging, one thing to
check: if the board is
enabled and a valid address for the board is on the bus, then U4 pin 8
should be high.
Hey cool, that's the kind of info I need to keep me going. I'll take a
look
at that in a bit.. or, take a look at that bit in a while or something.
So here's a question or two. First off, how do you pronounce a letter
designation with a line over it - like the outputs of a flip-flop are Q and
(Q with overline). Do you say "Q high" or "Q prime".. "Q
complement" or
what? What about when a named signal such as CLOC or PWR has an overline?
Do you pronounce it "CLOC active high" or something?
(Does that line actually mean "active high"? - that's what I've
surmised..)
Finally, on the CPU board, pin 49 supplies the CLOC signal.. but it's
actually pins 25 & 24 that the DRAM card look to for +its+ clock signal.
Those pins are marked with what looks like a ?-1 and ?-2 (Greek Phi),
respectively. Is that actually a 'phi', and if so, what does it mean - what
are those signals, if not clock signals? And how do you pronounce them? It
could be a slashed-zero, too... "?".
(Generally Theta (?) is used to denote a phase / angular relationship or
quantity. it looks kinda like phi, but it's not.)
As for my trainer, or "chip tester" as I call it.. the only bad parts are
the +/-15 (var.) supplies. IIRC, the outputs are just the wipers of 1/4W
200R pots. Need to look at that again, and maybe it's time to install some
low-dropout linear regs ala LT1084 in there. Get some kind of stability and
over-current protection - when I received it, one of those pots was smoked.
5:41 p.m.
Just noticed some errors in the CCS DRAM board schematic. Both U4 (74LS20)
and U5 (7400) are drawn as an OR gates. I'm sure there's more..
On Mon, Sep 1, 2014 at 7:28 PM, drlegendre . <drlegendre at gmail.com> wrote:
Thanks for the input again..
On Mon, Sep 1, 2014 at 6:21 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
I haven't examined the schematic in enough detail to quite convince
myself for sure the board will work without the RFSH signal, but that would
affect the writing/retention.
I'm a bit confused.. all DRAMs need a refresh, and the doc for this board
is pretty explicit that it needs "the correct" (ugh!) phase of the clock
signal "on pins 24 & 25". Why would you think the board doesn't
require
such a signal, that it has its own on-board refresh hardware? FWIW, there's
no crystal on-board to control an osc. to that level of precision.
To start in on board-level debugging, one thing
to check: if the board is
enabled and a valid address for the board is on the bus, then U4 pin 8
should be high.
Hey cool, that's the kind of info I need to keep me going. I'll take a
look at that in a bit.. or, take a look at that bit in a while or
something.
So here's a question or two. First off, how do you pronounce a letter
designation with a line over it - like the outputs of a flip-flop are Q and
(Q with overline). Do you say "Q high" or "Q prime".. "Q
complement" or
what? What about when a named signal such as CLOC or PWR has an overline?
Do you pronounce it "CLOC active high" or something?
(Does that line actually mean "active high"? - that's what I've
surmised..)
Finally, on the CPU board, pin 49 supplies the CLOC signal.. but it's
actually pins 25 & 24 that the DRAM card look to for +its+ clock signal.
Those pins are marked with what looks like a ?-1 and ?-2 (Greek Phi),
respectively. Is that actually a 'phi', and if so, what does it mean - what
are those signals, if not clock signals? And how do you pronounce them? It
could be a slashed-zero, too... "?".
(Generally Theta (?) is used to denote a phase / angular relationship or
quantity. it looks kinda like phi, but it's not.)
As for my trainer, or "chip tester" as I call it.. the only bad parts are
the +/-15 (var.) supplies. IIRC, the outputs are just the wipers of 1/4W
200R pots. Need to look at that again, and maybe it's time to install some
low-dropout linear regs ala LT1084 in there. Get some kind of stability and
over-current protection - when I received it, one of those pots was smoked.
6:06 p.m.
Sorry for the trickle, here, but I'm making progress and need to keep
things rolling.
So OK, I think I understand how the board enable/disable circuits work, now
that Brent tipped me off to U4. The output of U4 runs to one input of the
3-input NAND at U3. PHANTOM also comes in on U3, as does another signal
from the output of U7 I don't know. Point is, so
long as all of these 3
remain high, the output of U3 remains low. If any of the 3 go
low, output
of U3 goes high.
The output of U3 ties to the (overlined) OE (output enable?) of U20.. which
is a tri-state device. So if that input were to go high, then the outputs
of U20 all go high-Z and effectively cut-off lines DI0-DI7 to the RAM
matrix. I think DI=Data In, right? So in other words, if any of the 3
inputs to U3 goes low, the DI0-DI7 lines go high-Z and cutoff from the
buss..
Did I get that right?
On Mon, Sep 1, 2014 at 7:41 PM, drlegendre . <drlegendre at gmail.com> wrote:
Just noticed some errors in the CCS DRAM board
schematic. Both U4 (74LS20)
and U5 (7400) are drawn as an OR gates. I'm sure there's more..
On Mon, Sep 1, 2014 at 7:28 PM, drlegendre . <drlegendre at gmail.com> wrote:
Thanks for the input again..
On Mon, Sep 1, 2014 at 6:21 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
I haven't examined the schematic in enough detail to quite convince
myself for sure the board will work without the RFSH signal, but that would
affect the writing/retention.
I'm a bit confused.. all DRAMs need a refresh, and the doc for this board
is pretty explicit that it needs "the correct" (ugh!) phase of the clock
signal "on pins 24 & 25". Why would you think the board doesn't
require
such a signal, that it has its own on-board refresh hardware? FWIW, there's
no crystal on-board to control an osc. to that level of precision.
To start in on board-level debugging, one thing
to check: if the board
is enabled and a valid address for the board is on the bus, then U4 pin 8
should be high.
Hey cool, that's the kind of info I need to keep me going. I'll take a
look at that in a bit.. or, take a look at that bit in a while or
something.
So here's a question or two. First off, how do you pronounce a letter
designation with a line over it - like the outputs of a flip-flop are Q and
(Q with overline). Do you say "Q high" or "Q prime".. "Q
complement" or
what? What about when a named signal such as CLOC or PWR has an overline?
Do you pronounce it "CLOC active high" or something?
(Does that line actually mean "active high"? - that's what I've
surmised..)
Finally, on the CPU board, pin 49 supplies the CLOC signal.. but it's
actually pins 25 & 24 that the DRAM card look to for +its+ clock signal.
Those pins are marked with what looks like a ?-1 and ?-2 (Greek Phi),
respectively. Is that actually a 'phi', and if so, what does it mean - what
are those signals, if not clock signals? And how do you pronounce them? It
could be a slashed-zero, too... "?".
(Generally Theta (?) is used to denote a phase / angular relationship or
quantity. it looks kinda like phi, but it's not.)
As for my trainer, or "chip tester" as I call it.. the only bad parts are
the +/-15 (var.) supplies. IIRC, the outputs are just the wipers of 1/4W
200R pots. Need to look at that again, and maybe it's time to install some
low-dropout linear regs ala LT1084 in there. Get some kind of stability and
over-current protection - when I received it, one of those pots was smoked.
7:42 p.m.
On 2014-Sep-01, at 5:41 PM, drlegendre . wrote:
Just noticed some errors in the CCS DRAM board
schematic. Both U4 (74LS20)
and U5 (7400) are drawn as an OR gates. I'm sure there's more..
No they're not drawn incorrectly, they are drawn in their negative-logic formulation.
Think through the logic states of the inputs as they are drawn and you'll find
it's the same as the NAND gates you expect.
This is done to represent the functional intention of the logic design, which sometimes
doesn't mesh with the 'standard' (positive-logic) presentation.
U7 to the right however, actually is drawn incorrectly. It's a NOR gate, but the
intention is that of an AND gate with inverted inputs, except they forgot to draw the
inversion bubbles on the inputs.
On 2014-Sep-01, at 6:06 PM, drlegendre . wrote:
Sorry for the trickle, here, but I'm making
progress and need to keep
things rolling.
So OK, I think I understand how the board enable/disable circuits work, now
that Brent tipped me off to U4. The output of U4 runs to one input of the
3-input NAND at U3. PHANTOM also comes in on U3, as does another signal
from the output of U7 I don't know. Point is, so long as all of these 3
remain high, the output of U3 remains low. If any of the 3 go low, output
of U3 goes high.
The output of U3 ties to the (overlined) OE (output enable?) of U20.. which
is a tri-state device. So if that input were to go high, then the outputs
of U20 all go high-Z and effectively cut-off lines DI0-DI7 to the RAM
matrix. I think DI=Data In, right? So in other words, if any of the 3
inputs to U3 goes low, the DI0-DI7 lines go high-Z and cutoff from the
buss..
Did I get that right?
Yes.
And stated in the complement, all three inputs to U3 must be high for the mem board to put
data on the bus.
The third input (U7 from discussion above) is a combination of nMEMR and PDBIN, MEMR
indicates this is a memory read cycle, PDBIN is a strobe telling the mem board it can put
the data onto the bus now (while the strobe is active).
2 Sep
2 Sep
12:08 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Just noticed some errors in the CCS DRAM board schematic. Both U4 (74LS20)
and U5 (7400) are drawn as an OR gates. I'm sure there's more..
I've not seen the schamtics, but are they drawn, perhaps, as OR gates
_with inverting circles on the inputs_? Rememebr that a positive logic
AND gate is a negative logic OR gate (De Morgan's lwa, essentially). That
is, if you have 2 active low signals (signals that are true when low/0),
and feed them into am AND gate like a 7408, then output, if considerd
also to be actiuve low, is true is either of the inputs is true
(translation : the output of an AND gate is 0 if either of the inputs is
0). So calling it an OR gate makes sense.
-tony
3:12 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Howdy,
On Tue, Sep 2, 2014 at 2:08 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
Yes, drawn as an OR with inverter bubbles at the inputs.
Hmm.. negative logic vs. positive logic.. that's a new one to me. Sure, I
get what you're saying, but at my current level it really seems like an
unnecessary complication / confusion. The data sheet calls out the 7408 as
"quad AND gate", and that's how it behaves, so that's how I expect a
7408
to be drawn.. as AND gates.
As time goes on and experience grows, I'm sure the 'wisdom' of their
choices will become more evident. At the moment, it's a distraction.
So then, let's move on to the section on configuring the switches on the
board. Frankly, it appears not only confusing and just plain wrong, it also
appears to contradict itself. I think this is the stuff that Brent was
mentioning earlier - if you set those switches the way the doc indicates,
the memory gets mapped to the top-end of the 64K range, as opposed to the
bottom end. That one I verified. Also, the switches on the board are in
reverse order vs. the switch tables drawn in the manual.
Then there's the strange statement.. "closed=0 open=1", bottom of p.1-5.
Now that defies every convention known to man.. 0=false=open=off /
1=true=closed=on in my world.
(as ever, docs are at nerp.net/~legendre/altair/
Just noticed some errors in the CCS DRAM board schematic. Both U4
(74LS20)
and U5 (7400) are drawn as an OR gates. I'm
sure there's more..
I've not seen the schamtics, but are they drawn, perhaps, as OR gates
_with inverting circles on the inputs_? Rememebr that a positive logic
AND gate is a negative logic OR gate (De Morgan's lwa, essentially). That
is, if you have 2 active low signals (signals that are true when low/0),
and feed them into am AND gate like a 7408, then output, if considerd
also to be actiuve low, is true is either of the inputs is true
(translation : the output of an AND gate is 0 if either of the inputs is
0). So calling it an OR gate makes sense.
-tony
3:18 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
But on the bright side, this thing pretty much works!
Fixed the stuck-on LED, still need to do some debugging. Something is up
with the PROT function - the switch doesn't enable the LED (or protect the
memory) - but if you play around toggling with the PROT/UNPROT it will
suddenly scramble the machine's memory and set the CPU running wild. Very
weird, I need to look into that one next..
That said, it does run the sample code in the operator's manual just fine..
the little program that adds two numbers in 10000000 and 10000001 and
stores the result in 10000010. Ran it a dozen times with different values,
works as expected. And that's a major improvement. Basically, it seems that
the DRAM card was simply never being enabled for one reason or another.
?
5 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Thanks, Eric.. The assistance & education I received from folks like Brent
and yourself was truly invaluable.
This wasn't my first board-level digital experience - I did successfully
repair two C-64s and one 1541 floppy drive in the last couple of weeks -
but it was certainly the most extensive and in-depth project to-date. I'm a
little embarrassed to say it, but I actually acquired this 'kit' almost ten
years ago, as of this writing. It spent most of the time just getting
stored & shuffled around - I'll admit to being (somewhat correctly)
intimidated by the project.
If I'd tried this back when I got it, I'm not sure the outcome would have
been as good. More or less chipped-away at it for the last couple years,
did all the PSU work (stuff I can do in my sleep) about a year ago. I'd
decided to spend a little more time on it early this month - decided to
pre-cut the wiring for the board. But then I found I'd already done it, so
cripes.. I guess I'd run out of prep-work and it's +time to get down to
work and do the job+.
Anyway, I need to sort out a few things yet. I'm sure there will be a few
more questions. But really, the SRAM board was the real missing piece of
the puzzle - and I'd like to know why the DRAM is non-functional.. is the
board bad, or is it just incompatible?
Oh hey, and why does Tony type like that? Does he talk that way in the
flesh?
On Tue, Sep 2, 2014 at 6:05 PM, Eric Smith <spacewar at gmail.com> wrote:
On Tue, Sep 2, 2014 at 4:18 PM, drlegendre .
<drlegendre at gmail.com> wrote:
But on the bright side, this thing pretty much
works!
Congrats!
5:49 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 2014-Sep-02, at 3:12 PM, drlegendre . wrote:
So then, let's move on to the section on
configuring the switches on the
board. Frankly, it appears not only confusing and just plain wrong, it also
appears to contradict itself. I think this is the stuff that Brent was
mentioning earlier - if you set those switches the way the doc indicates,
the memory gets mapped to the top-end of the 64K range, as opposed to the
bottom end. That one I verified. Also, the switches on the board are in
reverse order vs. the switch tables drawn in the manual
It's confusing because:
- there's half-a-dozen levels of inversion going on in the circuitry,
- they installed some switches with the opposite open/closed orientation to that of the
design,
- and the off/on in the doc refers to the bit values, not the switch positions.
I think the four address-group switch-sets for your board should be:
UUDD DUDD UDDD DDDD
U = up, towards top edge of board
D = down, towards edge connector
The other small switch-set WA/BO/BD looks opposite to the doc too.
Then there's the strange statement..
"closed=0 open=1", bottom of p.1-5.
Now that defies every convention known to man.. 0=false=open=off /
1=true=closed=on in my world.
Sometimes the convention used in some field of study (boolean logic) doesn't match up
with a physical implementation (TTL electronics).
Closing the switch pulls the line low, to GND. This is standard with TTL because TTL is in
an implementation class of logic called current-sinking logic (look up a resource that
shows how TTL works electrically).
It's much more power-efficient to do it this way than the reverse. Also, sometimes
it's preferable to have one side of a switch at GND rather than +V.
Whether that closed switch is going to match or complement the '1' in an address
bit depends on how many inversions occur in the address comparison circuitry.
Anyways .. Yay! - a functioning Altair.
6:15 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Brent & All,
A big thanks to you, Brent.. you were a great help.
But yeah, the switch positions are essentially backwards from the
indications in the doc. I was able to sort that, but it's still kind of a
creepy feeling.. I sympathize for the (person like myself) 40 years ago
without any kind of experienced support & assistance on-tap. I've written
kit assembly & owners manuals for stuff that's more complex to build than
that board, and even I managed to get my ons and offs coherent and easily
understood!
I'm sure it's small potatoes for folks like yourself, but for me, this is a
big breakthrough.. some confirmatory evidence of my progress up the
learning curve. A couple more rounds like this, and I'll need some bigger
fish to fry.. then lookout, lol!
(Oh, and after reading about two dozen datasheets for 74XX I +do+ know how
TTL stuff is built, internally. Ain't nothing but xistors, diodes,
resistors and caps in there, for the most part. It could all be built from
basic discrete components - and more importantly, it once +was+. It's all
about the "I" in "IC", eh?)
On Tue, Sep 2, 2014 at 7:49 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Sep-02, at 3:12 PM, drlegendre . wrote:
So then, let's move on to the section on
configuring the switches on the
board. Frankly, it appears not only confusing and just plain wrong, it
also
appears to contradict itself. I think this is the
stuff that Brent was
mentioning earlier - if you set those switches the way the doc indicates,
the memory gets mapped to the top-end of the 64K range, as opposed to the
bottom end. That one I verified. Also, the switches on the board are in
reverse order vs. the switch tables drawn in the manual
It's confusing because:
- there's half-a-dozen levels of inversion going on in the circuitry,
- they installed some switches with the opposite open/closed orientation
to that of the design,
- and the off/on in the doc refers to the bit values, not the switch
positions.
I think the four address-group switch-sets for your board should be:
UUDD DUDD UDDD DDDD
U = up, towards top edge of board
D = down, towards edge connector
The other small switch-set WA/BO/BD looks opposite to the doc too.
Then there's the strange statement..
"closed=0 open=1", bottom of p.1-5.
Now that defies every convention known to man.. 0=false=open=off /
1=true=closed=on in my world.
Sometimes the convention used in some field of study (boolean logic)
doesn't match up with a physical implementation (TTL electronics).
Closing the switch pulls the line low, to GND. This is standard with TTL
because TTL is in an implementation class of logic called current-sinking
logic (look up a resource that shows how TTL works electrically).
It's much more power-efficient to do it this way than the reverse. Also,
sometimes it's preferable to have one side of a switch at GND rather than
+V.
Whether that closed switch is going to match or complement the '1' in an
address bit depends on how many inversions occur in the address comparison
circuitry.
Anyways .. Yay! - a functioning Altair.
7:12 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
And here's the next question.. it's about this PROT/UNPROT feature.. it's a
write-protect feature for the system RAM.
As noted earlier, all the control panel does is supply buffered signals
from the toggle switch to the mainboard, which must be
supported &
acknowledged by the memory board.
I don't see any connections to the relevant pins, on either the SD Systems
(DRAM) board or the CCS (SRAM) board, that would support this feature. So
the question is, is the memory protection feature some sort of proprietary
MITS / Altair feature that just wasn't picked up by 3rd party mfr's?
Would I expect to see protection implemented on the genuine MITS memory
boards - and not on 3rd party? Because it does seem that it's all up to the
board design as to whether or not this is supported. Come to think, I need
to look at the docs for the MITS 1K / 4K boards.
On Tue, Sep 2, 2014 at 8:15 PM, drlegendre . <drlegendre at gmail.com> wrote:
Brent & All,
A big thanks to you, Brent.. you were a great help.
But yeah, the switch positions are essentially backwards from the
indications in the doc. I was able to sort that, but it's still kind of a
creepy feeling.. I sympathize for the (person like myself) 40 years ago
without any kind of experienced support & assistance on-tap. I've written
kit assembly & owners manuals for stuff that's more complex to build than
that board, and even I managed to get my ons and offs coherent and easily
understood!
I'm sure it's small potatoes for folks like yourself, but for me, this is
a big breakthrough.. some confirmatory evidence of my progress up the
learning curve. A couple more rounds like this, and I'll need some bigger
fish to fry.. then lookout, lol!
(Oh, and after reading about two dozen datasheets for 74XX I +do+ know how
TTL stuff is built, internally. Ain't nothing but xistors, diodes,
resistors and caps in there, for the most part. It could all be built from
basic discrete components - and more importantly, it once +was+. It's all
about the "I" in "IC", eh?)
On Tue, Sep 2, 2014 at 7:49 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Sep-02, at 3:12 PM, drlegendre . wrote:
So then, let's move on to the section on
configuring the switches on the
board. Frankly, it appears not only confusing and just plain wrong, it
also
appears to contradict itself. I think this is the
stuff that Brent was
mentioning earlier - if you set those switches the way the doc
indicates,
the memory gets mapped to the top-end of the 64K
range, as opposed to
the
bottom end. That one I verified. Also, the
switches on the board are in
reverse order vs. the switch tables drawn in the manual
It's confusing because:
- there's half-a-dozen levels of inversion going on in the circuitry,
- they installed some switches with the opposite open/closed
orientation to that of the design,
- and the off/on in the doc refers to the bit values, not the switch
positions.
I think the four address-group switch-sets for your board should be:
UUDD DUDD UDDD DDDD
U = up, towards top edge of board
D = down, towards edge connector
The other small switch-set WA/BO/BD looks opposite to the doc too.
Then there's the strange statement..
"closed=0 open=1", bottom of p.1-5.
Now that defies every convention known to man.. 0=false=open=off /
1=true=closed=on in my world.
Sometimes the convention used in some field of study (boolean logic)
doesn't match up with a physical implementation (TTL electronics).
Closing the switch pulls the line low, to GND. This is standard with TTL
because TTL is in an implementation class of logic called current-sinking
logic (look up a resource that shows how TTL works electrically).
It's much more power-efficient to do it this way than the reverse. Also,
sometimes it's preferable to have one side of a switch at GND rather than
+V.
Whether that closed switch is going to match or complement the '1' in an
address bit depends on how many inversions occur in the address comparison
circuitry.
Anyways .. Yay! - a functioning Altair.
3 Sep
3 Sep
8:14 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Came across something else last night.. are the power transformers (in B
model PSUs) known to be a bit on the leaky side?
I was running the machine on a non-grounded outlet, and noticed quite a bit
of tingle along the metal chassis. Hooked up an instrument and read around
90uA of 60Hz AC leakage current between chassis and the cold-water pipe
ground circuit for my ESD protection scheme. (actually an iron radiator,
but it's a solid, galvanic earth ground - verified). And I heard bursts of
static on my 1941 Zenith AM set when I clipped / unclipped the chassis from
the cold-water ground.. you could actually see the arc jump if I killed the
room lights.
I found this while trying to t-shoot the PROT issue (where fiddling with
the switch would scramble the RAM, and send the CPU running wild). Turns
out that it wasn't just the PROT switch - any switch, or seemingly any
sufficient perturbation of the front panel could produce this same effect.
The panel wasn't secured by any nuts yet and was semi-free to move, as it's
all still in the debugging phase, so I went ahead and installed several
nuts (on switch shafts) to hold it down.
Since securing the panel, I haven't been able to reproduce the crazy
behavior. It might be that leakage EMF was occasionally finding a path from
chassis to panel, and tickling the logic enough to make it go wonky. In
fact, prior to securing the panel, if I rocked it back & forth (switch
ferrules grazing the holes on the chassis panel) it would also produce
static on the AM radio..
Does this seem typical, to be expected? It's a large transformer, after
all.. like 16-18lbs. And I sure don't know what else could be leaking like
that..
On another topic, this thing needs some inrush current limiting. If nothing
else, to give that poor bridge rect & 95,000uF 3" cap a smoother ride at
startup. It really surges when you flip the power switch 'on'. Keystone
CL-30, CL-90, something simple like that?
On Tue, Sep 2, 2014 at 9:12 PM, drlegendre . <drlegendre at gmail.com> wrote:
And here's the next question.. it's about this
PROT/UNPROT feature.. it's
a write-protect feature for the system RAM.
As noted earlier, all the control panel does is supply buffered signals
from the toggle switch to the mainboard, which must be supported &
acknowledged by the memory board.
I don't see any connections to the relevant pins, on either the SD Systems
(DRAM) board or the CCS (SRAM) board, that would support this feature. So
the question is, is the memory protection feature some sort of proprietary
MITS / Altair feature that just wasn't picked up by 3rd party mfr's?
Would I expect to see protection implemented on the genuine MITS memory
boards - and not on 3rd party? Because it does seem that it's all up to the
board design as to whether or not this is supported. Come to think, I need
to look at the docs for the MITS 1K / 4K boards.
On Tue, Sep 2, 2014 at 8:15 PM, drlegendre . <drlegendre at gmail.com> wrote:
Brent & All,
A big thanks to you, Brent.. you were a great help.
But yeah, the switch positions are essentially backwards from the
indications in the doc. I was able to sort that, but it's still kind of a
creepy feeling.. I sympathize for the (person like myself) 40 years ago
without any kind of experienced support & assistance on-tap. I've written
kit assembly & owners manuals for stuff that's more complex to build than
that board, and even I managed to get my ons and offs coherent and easily
understood!
I'm sure it's small potatoes for folks like yourself, but for me, this is
a big breakthrough.. some confirmatory evidence of my progress up the
learning curve. A couple more rounds like this, and I'll need some bigger
fish to fry.. then lookout, lol!
(Oh, and after reading about two dozen datasheets for 74XX I +do+ know
how TTL stuff is built, internally. Ain't nothing but xistors, diodes,
resistors and caps in there, for the most part. It could all be built from
basic discrete components - and more importantly, it once +was+. It's all
about the "I" in "IC", eh?)
On Tue, Sep 2, 2014 at 7:49 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Sep-02, at 3:12 PM, drlegendre . wrote:
So then, let's move on to the section on
configuring the switches on
the
board. Frankly, it appears not only confusing and
just plain wrong, it
also
appears to contradict itself. I think this is the
stuff that Brent was
mentioning earlier - if you set those switches the way the doc
indicates,
the memory gets mapped to the top-end of the 64K
range, as opposed to
the
bottom end. That one I verified. Also, the
switches on the board are in
reverse order vs. the switch tables drawn in the manual
It's confusing because:
- there's half-a-dozen levels of inversion going on in the circuitry,
- they installed some switches with the opposite open/closed
orientation to that of the design,
- and the off/on in the doc refers to the bit values, not the switch
positions.
I think the four address-group switch-sets for your board should be:
UUDD DUDD UDDD DDDD
U = up, towards top edge of board
D = down, towards edge connector
The other small switch-set WA/BO/BD looks opposite to the doc too.
Then there's the strange statement..
"closed=0 open=1", bottom of
p.1-5.
Now that defies every convention known to man..
0=false=open=off /
1=true=closed=on in my world.
Sometimes the convention used in some field of study (boolean logic)
doesn't match up with a physical implementation (TTL electronics).
Closing the switch pulls the line low, to GND. This is standard with TTL
because TTL is in an implementation class of logic called current-sinking
logic (look up a resource that shows how TTL works electrically).
It's much more power-efficient to do it this way than the reverse. Also,
sometimes it's preferable to have one side of a switch at GND rather than
+V.
Whether that closed switch is going to match or complement the '1' in an
address bit depends on how many inversions occur in the address comparison
circuitry.
Anyways .. Yay! - a functioning Altair.
9:33 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/03/2014 08:14 AM, drlegendre . wrote:
Came across something else last night.. are the power
transformers (in B
model PSUs) known to be a bit on the leaky side?
Does the PSU use capacitors to bypass RFI from the transformer to the
chassis? If so, there's probably your answer. Properly, those should
be Y-rated safety caps.
--Chuck
12:18 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 2014-Sep-03, at 9:33 AM, Chuck Guzis wrote:
On 09/03/2014 08:14 AM, drlegendre . wrote:
But note it doesn't necessarily mean the capacitors are bad or leaky. If the ground
lead is open, the common arrangement of line-filter caps (the two caps from line and
neutral to gnd) produces an AC voltage divider which will leave the chassis at 1/2*mains
VAC, e.g. 60 VAC in North America.
Any piece of equipment with the common line filter and a 3-lead (grounded) power cord
*needs* the ground connection.
Such caps have a high enough impedance at 60Hz that current is limited, but with the
ground lead open it's certainly enough to produce noise problems and perhaps a tingle
when touched.
Came across something else last night.. are the
power transformers (in B
model PSUs) known to be a bit on the leaky side?
Does the PSU use capacitors to bypass RFI from the transformer to the chassis? If so,
there's probably your answer. Properly, those should be Y-rated safety caps.
2:05 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Howdy Chuck,
On Wed, Sep 3, 2014 at 11:33 AM, Chuck Guzis <cclist at sydex.com> wrote:
On 09/03/2014 08:14 AM, drlegendre . wrote:
There is no AC mains-side bypass installed, of any type - nor is any shown
in the schematics. It probably won't hurt to install an X-type across the
line, though.. seems like the sort of thing it ought to have, eh?
I can mount one, once I decide what to do - if anything - to limit the
inrush current. From the data, it seems like the CL-60 might be the ticket
for this one.
Came across something else last night.. are the
power transformers (in B
model PSUs) known to be a bit on the leaky side?
Does the PSU use capacitors to bypass RFI from the transformer to the
chassis? If so, there's probably your answer. Properly, those should be
Y-rated safety caps.
--Chuck
2:53 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/03/2014 02:05 PM, drlegendre . wrote:
There is no AC mains-side bypass installed, of any
type - nor is any shown
in the schematics. It probably won't hurt to install an X-type across the
line, though.. seems like the sort of thing it ought to have, eh?
It probably wouldn't hurt to cut down on some RFI. That baeing said, is
your chassis connected to the line safety ground? (that is, is the
ground lead in your line cord firmly connected to the chassis? It is on
my 8800). If you wanted to use a made-for-purpose unit, you could use
one of the packaged "bathtub"-style AC line filters.
I can mount one, once I decide what to do - if
anything - to limit the
inrush current. From the data, it seems like the CL-60 might be the ticket
for this one.
The original 8800 supply is a piece of under-capacity slapdash design,
IMO. There are many better designs. My S100 Integrand box has a power
transformer that you could probably arc-weld with.
--Chuck
3:59 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Chuck,
This box was upgraded to the 'B' supply - so it has one very large xfmr in
it, with three secondaries. The +8V line is rectified by a 35A part, into a
95,000uF computer-grade cap.
The +/-18V lines use a modern bridge, and 4400uF of new low-ESR filter caps
at the inputs. Regulation is by new LM7818 / 7918 1.5A regs, w/heat sinks,
and 22uF + 0.47uF (film) bypass at the outputs.
So it's about as modernized as it's gonna get, while still using the legacy
transformer.. you still consider that under-rated?
On Wed, Sep 3, 2014 at 4:53 PM, Chuck Guzis <cclist at sydex.com> wrote:
On 09/03/2014 02:05 PM, drlegendre . wrote:
There is no AC mains-side bypass installed, of any type - nor is any shown
in the schematics. It probably won't hurt to
install an X-type across the
line, though.. seems like the sort of thing it ought to have, eh?
It probably wouldn't hurt to cut down on some RFI. That baeing said, is
your chassis connected to the line safety ground? (that is, is the ground
lead in your line cord firmly connected to the chassis? It is on my
8800). If you wanted to use a made-for-purpose unit, you could use one of
the packaged "bathtub"-style AC line filters.
I can mount one, once I decide what to do - if anything - to limit the
inrush current. From the data, it seems like the
CL-60 might be the ticket
for this one.
The original 8800 supply is a piece of under-capacity slapdash design,
IMO. There are many better designs. My S100 Integrand box has a power
transformer that you could probably arc-weld with.
--Chuck
4:52 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/03/2014 03:59 PM, drlegendre . wrote:
This box was upgraded to the 'B' supply - so
it has one very large xfmr in
it, with three secondaries. The +8V line is rectified by a 35A part, into a
95,000uF computer-grade cap.
The +/-18V lines use a modern bridge, and 4400uF of new low-ESR filter caps
at the inputs. Regulation is by new LM7818 / 7918 1.5A regs, w/heat sinks,
and 22uF + 0.47uF (film) bypass at the outputs.
So it's about as modernized as it's gonna get, while still using the legacy
transformer.. you still consider that under-rated?
Well, I can't say--I dropped using the 8800 in favor of an IMSAI 8080 at
the time and then later, my Integrand box.
So the 8800 has been on the shelf all this time. I haven't even tried
powering it up in perhaps 20-25 years.
--Chuck
7:10 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Hi Chuck,
On Wed, Sep 3, 2014 at 6:52 PM, Chuck Guzis <cclist at sydex.com> wrote:
Well, I can't say--I dropped using the 8800 in favor of an IMSAI 8080 at
the time and then later, my Integrand box.
So the 8800 has been on the shelf all this time. I haven't even tried
powering it up in perhaps 20-25 years.
Well, if it's no further use to you, I'd be happy to take it under my
wing.. ;-)
But really, I am still looking for a MITS 1K SRAM card for it.. just to put
the bug in your ear if you didn't see those earlier posts of mine. It's
really the last piece of the puzzle.. unless I can drum up an original 2 or
4-slot mainboard, or "expander board" as I think MITS termed it.
10:08 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/03/2014 07:10 PM, drlegendre . wrote:
But really, I am still looking for a MITS 1K SRAM card
for it.. just to put
the bug in your ear if you didn't see those earlier posts of mine. It's
really the last piece of the puzzle.. unless I can drum up an original 2 or
4-slot mainboard, or "expander board" as I think MITS termed it.
If you don't mind the asking, why that particular card? It can't be for
the utility--1K isn't enough to do much in. You could always wire one
up yourself--I think Andrew did some S100 prototype cards. Like a lot
of other folks, I have a barrel of 2Kx8 SRAMs here.
--Chuck
4 Sep
4 Sep
8:27 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Hi Chuck,
On Thu, Sep 4, 2014 at 12:08 AM, Chuck Guzis <cclist at sydex.com> wrote:
On 09/03/2014 07:10 PM, drlegendre . wrote:
If you don't mind the asking, why that particular card? It can't be for
the utility--1K isn't enough to do much in. You could always wire one up
yourself--I think Andrew did some S100 prototype cards. Like a lot of
other folks, I have a barrel of 2Kx8 SRAMs here.
Heh, 1K seems like plenty to me, when the only I/O method is a bank of 24
toggle switches and 30 LEDs. ;-)
Really though, while that's true, it's more about originality. The goal
here is to set the machine back to where it was when it was first built
from a kit, in 1975 or so. The rest of it is still
pretty much intact, save
the "B" PSU mods. Not only would those changes be
very hard to revert, but
they both period-correct -and- genuine MITS parts.
In fact - though I need to confirm this - this kit may have been ordered
new with the B option PSU. I say this, as I know fully well who built the
machine, and I'm very familiar with this individuals general level of
workmanship. I'll be kind and say that it's known to be "a little
slipshod". But the work done installing the B mod, particularly the square
hole cut in the case for the fan, look like factory work to me.
Once the restoration is complete, I'll contact him and see what he
remembers about the machine's early days. One thing four sure, the
original 1K RAM board is lost to time.. he mentioned that.
10:48 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/04/2014 08:27 AM, drlegendre . wrote:
Really though, while that's true, it's more
about originality. The goal
here is to set the machine back to where it was when it was first built
from a kit, in 1975 or so. The rest of it is still pretty much intact, save
the "B" PSU mods. Not only would those changes be very hard to revert, but
they both period-correct -and- genuine MITS parts.
Maybe, but I think the best-selling 8800 kit was the special
introductory deal--CPU board, 2 4K DRAM boards and SIO for $1K. That's
what grabbed my attention and I'm sure that I wasn't the only one.
I picked up the acoustic coupler from a surplus TI Silent 700 parts
seller, made a power supply for it and wired it into the SIO using a
swtich to toggle between it and my TVT. Stored my files on the
mainframe at work. Eventually rigged up a cheap audio cassette recorder
to the modem and I was in business.
I don't know if a 1K RAM board with no serial I/O would have attracted
me even at $500.
--Chuck
noon
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 2014-Sep-04, at 10:48 AM, Chuck Guzis wrote:
On 09/04/2014 08:27 AM, drlegendre . wrote:
There's a Processor Technology 4K SRAM board with 1975 date codes on the ICs on ebay
right now.
http://www.ebay.com/itm/Processor-Technology-4K-RAM-S-100-board-ships-world…
It's 120$ though, which (shockingly) seems to be the median price for S100 boards on
ebay.
It's not MITS but it's very period-correct for the Altair. According to
s100computers.com it was targeted for the Altair.
http://www.s100computers.com/Hardware%20Folder/Processor%20Technology/Histo…
There are a couple of Altair 4K DRAM boards on ebay too, at ridiculous prices.
I wonder how much it would take to mod one to make it reliable.
Really though, while that's true, it's
more about originality. The goal
here is to set the machine back to where it was when it was first built
from a kit, in 1975 or so. The rest of it is still pretty much intact, save
the "B" PSU mods. Not only would those changes be very hard to revert, but
they both period-correct -and- genuine MITS parts.
Maybe, but I think the best-selling 8800 kit was the special introductory deal--CPU
board, 2 4K DRAM boards and SIO for $1K. That's what grabbed my attention and I'm
sure that I wasn't the only one.
I picked up the acoustic coupler from a surplus TI Silent 700 parts seller, made a power
supply for it and wired it into the SIO using a swtich to toggle between it and my TVT.
Stored my files on the mainframe at work. Eventually rigged up a cheap audio cassette
recorder to the modem and I was in business.
I don't know if a 1K RAM board with no serial I/O would have attracted me even at
$500.
1:23 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Hi Brent,
On Thu, Sep 4, 2014 at 2:00 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
There's a Processor Technology 4K SRAM board with 1975 date codes on the
ICs on ebay right now.
http://www.ebay.com/itm/Processor-Technology-4K-RAM-S-100-board-ships-world…
It's 120$ though, which (shockingly) seems to be the median price for S100
boards on ebay.
I saw those Processor Tech. boards as well, but took a pass.. cash for this
kind of thing is -tight- and I'm just going to hold out for the part I
want.. MITS 1K or 4K.
And yes, while the prices are pretty silly-high for S100 RAM boards, they
don't seem to actually sell for those prices all that often. As an
anecdote, the guy who sold me the CCS 16K SRAM board said he's sold a few
dozen S100 boards in the last year or so, and mine was among the last he
had.
That board cost $30 including USPS Priority 2-Day and it's in +mint+ shape,
and apparently full working order.
If he has that much experience selling these items, and was happy to take
$30 for one, I think that says something about the actual fair-market
value.. as ever, there's no shortage of dreamers with dollar signs in their
eyes on eBay.
3 Sep
3 Sep
12:15 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Came across something else last night.. are the power transformers (in B
model PSUs) known to be a bit on the leaky side?
I was running the machine on a non-grounded outlet, and noticed quite a bit
of tingle along the metal chassis. Hooked up an instrument and read around
90uA of 60Hz AC leakage current between chassis and the cold-water pipe
ground circuit for my ESD protection scheme. (actually an iron radiator,
Is there a amins filter circuit in this machine? This would often involve
capacitors between the AC lines and the chassis/gorund, so if the chassis
is not conencted to ground yo can draw a currnet form the live ('hot')
side of the mains thoough one of the capacitors to the chassis and then
to gorund.
Note that htis does not mean the capacitor is leaky. A capacitor will pass
an AC current, which is what the mains is.
-tony
2:43 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Hi Tony,
On Wed, Sep 3, 2014 at 2:15 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
Is there a amins filter circuit in this machine?
Nope.
Note that htis does not mean the capacitor is leaky. A capacitor will pass
an AC current, which is what the mains is.
Bear in mind, that while the workings of board-level digital circuits are
still
fairly new territory to me, I do have 20 yrs. experience as a
general-purpose electrical / electronic technician, mostly in the field of
analog / vacuum tube audio, radio and vehicle electrical systems. These
days, I specialize in cal & repair of vacuum tube testers and other older,
tube-based instruments.
4 Sep
4 Sep
11:45 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Hi Tony,
On Wed, Sep 3, 2014 at 2:15 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
Remember a mains filter could be part of the mains input conenctor. If
it's an IEC 320 type (the 'kettle plug' as used on PCs, etc) look at the
iback of the plug. a metal box there is oftne a mains filter.
If not, then I would disconenct the transformer primary and secondary
leads. Use a 'megger' (HV isulation tester) with a test votlage of 500V
or 100V on the mains input circuit (that is, between the live and neutral
input wires conencted together and the case) to check the inoput
conenctor, fusehold, switch, etc. Then use the megger to test between the
transformer primary widing and the core and then betwene the priamry
windign and the econdaries.
Hopefully it will not be thr transformer. I've had a surpsing number of
switches go leaky over the years.
Is there a amins filter circuit in this machine?
Nope.
Note that htis does not mean the capacitor is leaky. A capacitor will pass
an AC current, which is what the mains is.
Bear in mind, that while the workings of board-level digital circuits are
still
fairly new territory to me, I do have 20 yrs. experience as a
general-purpose electrical / electronic technician, mostly in the field of
analog / vacuum tube audio, radio and vehicle electrical systems. These
days, I specialize in cal & repair of vacuum tube testers and other older,
tube-based instruments.
1:39 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Hi Tony,
On Thu, Sep 4, 2014 at 1:45 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
Err.. yes.. I'm not sure what your point is? :-)
> Seoncdly, and more inportantly, the power supply is as 'aanlogue' as you
> can get. Forget that it powers a computer, treat it like the PSU in an
> audio amplifier. There is no real difference.
> Again, yes.. did something I said give you
the impression that I thought
otherwise? If you read my earlier posts, I specifically mentioned that I
had the PSU stuff taken care of months ago, as it's the sort of work I can
do in my sleep..
But it +has+ been a +while+ since I worked with a PSU that was driven by
such a large EI core xfmr. So I was asking if the ~85uA (that's micro-amps)
of leakage I measured would be typical for iron of that mass (18lbs or so)
and age. Virtually all (if not _all_) transformers exhibit some leakage -
it's just the nature of the beast. Stray capacitances in the xfmr provide a
coupling path for AC voltage, in addition to the other leakage paths which
can develop (due to imperfect insulation, etc).
Remember a mains filter could be part of the mains input conenctor.
Yes, I'm +fully+ aware of the integrated line filter / IEC mains socket
devices. It doesn't have one, I promise you.. ;-)
If it's an IEC 320 type (the 'kettle plug'
as used on PCs, etc)
It doesn't. It's just a hardwired cord with the typical black Heyco grommet
securing it in the case.
If not, then I would disconenct the transformer
primary and secondary
leads. Use a 'megger' (HV isulation tester) (...)
I have experience with these instruments, I've used them to test products
at a previous workplace..
Hopefully it will not be thr transformer. I've had
a surpsing number of
switches go leaky over the years.
There is presently no on-board switch, it's hardwired 'on'. Switching is
being done at the Variac.
Firstly, 'Digital circuits are built from analugue parts'.
5 Sep
5 Sep
12:37 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
If not, then I
would disconenct the transformer primary and secondary
leads. Use a 'megger' (HV isulation tester) (...)
I have experience with these instruments, I've used them to test products
at a previous workplace.. Hopefully it will not be thr transformer.
I've had a surpsing number of
switches go leaky over the years.
There is presently no on-board switch, it's hardwired 'on'. Switching is
being done at the Variac.
Firstly, 'Digital circuits are built from analugue parts'.
Err.. yes.. I'm not sure what your point is? :-)
Basically,m if you undersatand eaanluge electronics then you can
understnad digital. In fact my expeirence is that the hardest part of a
digital ssytem to design proeprly are the interconnecxtions, which should
be designed as (analgoue) transmission lines
Seoncdly, and more inportantly, the power supply
is as 'aanlogue' as you
can get. Forget that it powers a computer, treat it like the PSU in an
audio amplifier. There is no real difference.
Again, yes.. did something I said give you the impression that I thought
otherwise? If you read my earlier posts, I specifically mentioned that I
had the PSU stuff taken care of months ago, as it's the sort of work I can
do in my sleep..
But it +has+ been a +while+ since I worked with a PSU that was driven by
such a large EI core xfmr. So I was asking if the ~85uA (that's micro-amps)
of leakage I measured would be typical for iron of that mass (18lbs or so)
and age. Virtually all (if not _all_) transformers exhibit some leakage -
it's just the nature of the beast. Stray capacitances in the xfmr provide a
coupling path for AC voltage, in addition to the other leakage paths which
can develop (due to imperfect insulation, etc).
Sure. Which is why a DC inslation test (and note that some 'meggers' use
AC) is worth doing. This will distinguish between an inslation problem
(which will pass DC) and stra cpacitance (which won't).
Now lte'#s see...
85uA at 11)V, say is a resistance/impedance of about 1.3MOhms. At 60Hz,
that would seem to correspond to the reactance of a 2 nF capacitor (check
this, I may have made a mistake in the calculation). That sounds high for
a 'stray' to me.
-tony
1:28 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Sep 5, 2014, at 3:37 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
2 nF is what I get, too. That wouldn?t be stray capacitance in the transformer. But it
could be an EMI filter capacitor, if the PSU has such things. A DC test would sort that
out.
paul
...
But it +has+ been a +while+ since I worked with a PSU that was driven by
such a large EI core xfmr. So I was asking if the ~85uA (that's micro-amps)
of leakage I measured would be typical for iron of that mass (18lbs or so)
and age. Virtually all (if not _all_) transformers exhibit some leakage -
it's just the nature of the beast. Stray capacitances in the xfmr provide a
coupling path for AC voltage, in addition to the other leakage paths which
can develop (due to imperfect insulation, etc).
Sure. Which is why a DC inslation test (and note that some 'meggers' use
AC) is worth doing. This will distinguish between an inslation problem
(which will pass DC) and stra cpacitance (which won't).
Now lte'#s see...
85uA at 11)V, say is a resistance/impedance of about 1.3MOhms. At 60Hz,
that would seem to correspond to the reactance of a 2 nF capacitor (check
this, I may have made a mistake in the calculation). That sounds high for
a 'stray' to me.
2:23 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/05/2014 01:28 PM, Paul Koning wrote:
2 nF is what I get, too. That wouldn?t be stray
capacitance in the
transformer. But it could be an EMI filter capacitor, if the PSU has
such things. A DC test would sort that out.
Regardless, it doesn't answer the question about why the chassis isn't
grounded. The 8800 was most certainly equipped with a 3-conductor line
cord.
--Chuck
3:30 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Chuck & All,
On Fri, Sep 5, 2014 at 4:23 PM, Chuck Guzis <cclist at sydex.com> wrote:
Regardless, it doesn't answer the question about why the chassis isn't
grounded. The 8800 was most certainly equipped with a 3-conductor line
cord.
You'll have to look up a bit for the answer.
The chassis most certainly +does+ have a 3-wire cord, and it's properly
connected. Thing is, I live in a really old house (for the USA, anyway) and
it turns out that one of the circuits that's near my workbench doesn't
actually have a ground wire - and it turns out that's the circuit which was
being used to power the Variac which in turn powers the Altair.
I only discovered this issue last week, in the process of working on the
Altair, when I felt that tell-tale buzz on my fingertips as they happened
to lightly graze the chassis at one point. Same feel you get from a vintage
amp with a 2-wire cord and an AC line bypass to chassis.. the so-called
"Death Cap", in the lingo of some guitar doofuses who don't seem to grasp
the concept of impedances, and how little current that 50-100nF cap can
actually pass through the resistance of a human body at 60hz.
But it did make it easy to measure the leakage current.. just connect the
ammeter from chassis to the ESD ground jack on the bench.
Until I move it to a new circuit, I've got a heavy-duty clip lead tying the
Altair chassis to that same ESD ground jack.
4:16 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/05/2014 03:30 PM, drlegendre . wrote:
I only discovered this issue last week, in the process
of working on the
Altair, when I felt that tell-tale buzz on my fingertips as they happened
to lightly graze the chassis at one point. Same feel you get from a vintage
amp with a 2-wire cord and an AC line bypass to chassis.. the so-called
"Death Cap", in the lingo of some guitar doofuses who don't seem to grasp
the concept of impedances, and how little current that 50-100nF cap can
actually pass through the resistance of a human body at 60hz.
A bit of advice--when you do get it right, please also install a ground
fault interrupter also. We want you around for a few more years.
FWIW, I've got an industrial PC supply that will get me a little
"tingle" if not properly grounded, so perhaps what you're seeing isn't
that uncommon.
At any rate, I don't think you need to worry about 90 microamps leakage.
Most US GFCIs don't trip until the leakage current is somewhere around
6 ma--or about 60 times what you're seeing.
--Chuck
4:29 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Fri, Sep 5, 2014 at 5:16 PM, Chuck Guzis <cclist at sydex.com> wrote:
A bit of advice--when you do get it right, please also
install a ground
fault interrupter also. We want you around for a few more years.
Note that code allows for ungrounded three-prong outlets with GFCI.
Having a proper ground is still better, even with the GFCI.
4:32 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Fri, Sep 5, 2014 at 5:29 PM, Eric Smith <spacewar at gmail.com> wrote:
Note that code allows for ungrounded three-prong
outlets with GFCI.
I forgot to mention that in that case, code requires that you mark the
GFCI outlet "no equipment ground". It also has to be marked "GFCI
protected", but that marking should be present when you purchase the
outlet.
6:19 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/05/2014 04:32 PM, Eric Smith wrote:
I forgot to mention that in that case, code requires
that you mark the
GFCI outlet "no equipment ground". It also has to be marked "GFCI
protected", but that marking should be present when you purchase the
outlet.
I seem to recall something odd about NEC requirements for earth ground.
I seem to remember (and this is from long ago, so it's probably wrong)
that you get to drive one ground rod into the ground and if it measures
more than 600 ohms to line neutral, you can drive another one into the
ground and add it. After that, code is silent as to what to do next.
This can be a problem in dry, sandy soils.
It just seemed a bit odd to me that code didn't require more than just
the two attempts to get a good earth ground.
--Chuck
6:50 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Fri, Sep 5, 2014 at 8:19 PM, Chuck Guzis <cclist at sydex.com> wrote:
I seem to recall something odd about NEC requirements for earth ground. I
seem to remember (and this is from long ago, so it's probably wrong) that
you get to drive one ground rod into the ground and if it measures more
than 600 ohms to line neutral, you can drive another one into the ground
and add it. After that, code is silent as to what to do next. This can be
a problem in dry, sandy soils.
It just seemed a bit odd to me that code didn't require more than just the
two attempts to get a good earth ground.
That was after they removed the language about having a pack of hunting
dogs
urinate near the ground point until the resistance falls into spec.
Don't recall who was behind the change.. animal rights folks, trade unions,
communists, something like that.
10 Sep
10 Sep
12:35 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Fri, 5 Sep 2014, drlegendre . wrote:
On Fri, Sep 5, 2014 at 8:19 PM, Chuck Guzis <cclist
at sydex.com> wrote:
You left out the "politically correct" crowd. They've been responsible for
similar wording changes to the NEC in recent times.
I seem to recall something odd about NEC
requirements for earth ground. I
seem to remember (and this is from long ago, so it's probably wrong) that
you get to drive one ground rod into the ground and if it measures more
than 600 ohms to line neutral, you can drive another one into the ground
and add it. After that, code is silent as to what to do next. This can be
a problem in dry, sandy soils.
It just seemed a bit odd to me that code didn't require more than just the
two attempts to get a good earth ground.
That was after they removed the language about having a pack of hunting
dogs urinate near the ground point until the resistance falls into spec.
Don't recall who was behind the change.. animal rights folks, trade
unions, communists, something like that.
1:01 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Fri, 5 Sep 2014, Chuck Guzis wrote:
On 09/05/2014 04:32 PM, Eric Smith wrote:
NEC 250.56
If a single grounding electrode (rod, pipe, plate) does not have a
resistance to ground of 25 ohms or less, the NEC requires you to install a
second electrode at least 6ft apart from the first. If the calculated
parallel resistance of the two electrodes is still not 25 ohms or less
(they have to be disconnected from each other and measured separately),
the NEC does not require you to install any additional electrodes or
attempt to lower the resistance to ground.
In common practice, you usually just install two rod electrodes at a
/minimum/ of 6ft apart (12 feet or more is better) and don't even bother
checking the resistance to ground. It is usually just faster and easier to
just install two rod electrodes than to measure the electrode to ground
resistance with a 3-point fall of potential meter.
I forgot to mention that in that case, code
requires that you mark the
GFCI outlet "no equipment ground". It also has to be marked "GFCI
protected", but that marking should be present when you purchase the
outlet.
I seem to recall something odd about NEC requirements for earth ground.
I seem to remember (and this is from long ago, so it's probably wrong)
that you get to drive one ground rod into the ground and if it measures
more than 600 ohms to line neutral, you can drive another one into the
ground and add it. After that, code is silent as to what to do next.
This can be a problem in dry, sandy soils. It just seemed a bit odd to me that code didn't
require more than just
the two attempts to get a good earth ground.
Likely due to diminishing return. Adding yet another electrode isn't going
to help very much. In specialty applications where a low resistance ground
is required (radio communications for example), they make special chemical
type ground rods. It is also common to install large ground rings in these
sorts of applications.
6:48 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Sep 10, 2014, at 4:01 AM, Tothwolf <tothwolf at concentric.net> wrote:
...
One of the most interesting, and straightforward, high performance grounds is the Ufer
ground. It?s nothing more than a wire embedded in a couple of inches of concrete, fairly
long (20 or 30 feet?) and buried in the soil. Apparently this works very well even in
lousy soil. As I understand it, the fact that concrete absorbs water and is alkaline is
part of the reason. I learned about this from some professional lightning protection
literature. The technology goes back to 1940 or so.
paul
It just seemed a bit odd to me that code
didn't require more than just the two attempts to get a good earth ground.
Likely due to diminishing return. Adding yet another electrode isn't going to help
very much. In specialty applications where a low resistance ground is required (radio
communications for example), they make special chemical type ground rods. It is also
common to install large ground rings in these sorts of applications.
9:03 a.m.
New subject: Earth ground: was: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/10/2014 01:01 AM, Tothwolf wrote:
Likely due to diminishing return. Adding yet another
electrode isn't
going to help very much. In specialty applications where a low
resistance ground is required (radio communications for example), they
make special chemical type ground rods. It is also common to install
large ground rings in these sorts of applications.
Okay, so it's 25 ohms or less, so my memory isn't too bad. ;)
I recall this because the subject of well casings (normally galvanized
iron pipe) came up at one point in my life. I'd asked the local
inspector if it was permissible to use a deep well casing as earth
ground instead of the usual grounding rod if the well resistance to
earth ground was lower. His response was "no--it is the wrong material"
--Chuck
9:56 a.m.
New subject: Earth ground: was: Questions - Setting up a SRAM board in S-100 / Altair system?
On Sep 10, 2014, at 12:03 PM, Chuck Guzis <cclist at sydex.com> wrote:
On 09/10/2014 01:01 AM, Tothwolf wrote:
Interesting. But ?in addition to? is ok, if I remember right, and is in fact a very good
idea because it may prevent lightning damage to your well pump.
paul
Likely due to diminishing return. Adding yet
another electrode isn't
going to help very much. In specialty applications where a low
resistance ground is required (radio communications for example), they
make special chemical type ground rods. It is also common to install
large ground rings in these sorts of applications.
Okay, so it's 25 ohms or less, so my memory isn't too bad. ;)
I recall this because the subject of well casings (normally galvanized iron pipe) came up
at one point in my life. I'd asked the local inspector if it was permissible to use a
deep well casing as earth ground instead of the usual grounding rod if the well resistance
to earth ground was lower. His response was "no--it is the wrong material"
11:05 a.m.
New subject: Earth ground: was: Questions - Setting up a SRAM board in S-100 / Altair system?
On 09/10/2014 09:56 AM, Paul Koning wrote:
Interesting. But ?in addition to? is ok, if I
remember right, and is in fact a very good idea because it may prevent lightning damage to
your well pump.
Fortunately, lightning is a very rare occasion here. I don't remember
when there was a lightning strike of any sort in my area. Happens
mostly up in the mountains.
--Chuck
6:28 p.m.
New subject: Earth ground: was: Questions - Setting up a SRAM board in S-100 / Altair system?
Actually, a very informative discussion.
And nobody has yet suggested a mother-in-law standing in a bucket of
water.
6:54 p.m.
New subject: Earth ground: was: Questions - Setting up a SRAM board in S-100 / Altair system?
On 9/10/2014 7:28 PM, Fred Cisin wrote:
Actually, a very informative discussion.
And nobody has yet suggested a mother-in-law standing in a bucket of
water.
You want to face a *LIVE* WET MOTHER-IN-LAW!
Ben.
5 Sep
5 Sep
7:01 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Sep 5, 2014, at 19:32, Eric Smith <spacewar at gmail.com> wrote:
Yes, but if you're passing a standard outlet through a
GFCI outlet (which gives the same protection to the
downstream outlet), they aren't marked. The GFCI
outlets I just installed in my basement came with a page
of stickers with both the "GFCI protected" and "no
equipment ground" messages.
- Dave
On Fri, Sep 5, 2014 at 5:29 PM, Eric Smith
<spacewar at gmail.com> wrote:
Note that code allows for ungrounded three-prong outlets with GFCI.
I forgot to mention that in that case, code requires that you mark the
GFCI outlet "no equipment ground". It also has to be marked "GFCI
protected", but that marking should be present when you purchase the
outlet.
6 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Eric & All,
On Fri, Sep 5, 2014 at 6:29 PM, Eric Smith <spacewar at gmail.com> wrote:
On Fri, Sep 5, 2014 at 5:16 PM, Chuck Guzis <cclist
at sydex.com> wrote:
Your statement made me think for a moment.. and it became clear that I must
not fully understand the function of GFCI hardware.
Now if a GFI can operate on an outlet with n/c to the 3rd prong (read: no
ground wire) that +must+ mean that the GFI can sense a situation where a
first current I is flowing in the hot lead (black) but it's not equal to a
second current I' that is flowing in the neutral (white).
An example would be a radio that draws 500mA under normal conditions, where
500mA flows in both the hot & neutral. But if the radio falls in the
bathtub, now we might see a current of 750mA flowing in the hot, but only
500mA flowing in the neutral and an additional, anomalous 250mA flowing
"somewhere" - which in this case, would be through the water / human to the
cold-water pipe ground (via a metal tub, or metal drain hookup, etc).
So a GFI doesn't respond to currents flowing through the ground circuit,
but to current differentials in the hot & neutral circuits - is that
correct? If that's true, then it doesn't really matter what's going on in
the ground circuit - so long as the Ineutral < Ihot there's a fault
condition.. there's a current going somewhere it's not intended to flow, eh?
A bit of advice--when you do get it right, please
also install a ground
fault interrupter also. We want you around for a few more years.
Note that code allows for ungrounded three-prong outlets with GFCI.
Having a proper ground is still better, even with the GFCI.
6:59 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On 2014-Sep-05, at 6:00 PM, drlegendre . wrote:
Eric & All,
On Fri, Sep 5, 2014 at 6:29 PM, Eric Smith <spacewar at gmail.com> wrote:
Yes, that's what a GFCI does.
Inside the GFCI, the hot and neutral are sent through dual primaries (a turn or two each
on a toroid core) of a current sense transformer, connected such that the currents are in
opposition. A third - sense - winding feeds an an op-amp and thence the circuit-trip
relay. If the currents in the hot and neutral are in balance (equal) they cancel and
nothing is induced in the sense/secondary. If out of balance the difference induces V in
the sense winding, which trips the circuit open.
The same principle works for three phase, with all three (or four) current-carrying wires
going through the transformer.
On Fri, Sep 5, 2014 at 5:16 PM, Chuck Guzis
<cclist at sydex.com> wrote:
Your statement made me think for a moment.. and it became clear that I must
not fully understand the function of GFCI hardware.
Now if a GFI can operate on an outlet with n/c to the 3rd prong (read: no
ground wire) that +must+ mean that the GFI can sense a situation where a
first current I is flowing in the hot lead (black) but it's not equal to a
second current I' that is flowing in the neutral (white).
An example would be a radio that draws 500mA under normal conditions, where
500mA flows in both the hot & neutral. But if the radio falls in the
bathtub, now we might see a current of 750mA flowing in the hot, but only
500mA flowing in the neutral and an additional, anomalous 250mA flowing
"somewhere" - which in this case, would be through the water / human to the
cold-water pipe ground (via a metal tub, or metal drain hookup, etc).
So a GFI doesn't respond to currents flowing through the ground circuit,
but to current differentials in the hot & neutral circuits - is that
correct? If that's true, then it doesn't really matter what's going on in
the ground circuit - so long as the Ineutral < Ihot there's a fault
condition.. there's a current going somewhere it's not intended to flow, eh?
A bit of advice--when you do get it right, please
also install a ground
fault interrupter also. We want you around for a few more years.
Note that code allows for ungrounded three-prong outlets with GFCI.
Having a proper ground is still better, even with the GFCI.
9:44 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Hi Brent,
On Fri, Sep 5, 2014 at 8:59 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
Yes, that's what a GFCI does.
Inside the GFCI, the hot and neutral are sent through dual primaries (a
turn or two each on a toroid core) of a current sense transformer,
connected such that the currents are in opposition. A third - sense -
winding feeds an an op-amp and thence the circuit-trip relay. If the
currents in the hot and neutral are in balance (equal) they cancel and
nothing is induced in the sense/secondary. If out of balance the difference
induces V in the sense winding, which trips the circuit open.
The same principle works for three phase, with all three (or four)
current-carrying wires going through the transformer.
Hey cool, I actually figured that out on the fly..
The counter-phase windings with the tertiary 'sense' winding makes perfect
sense. I hadn't made it quite that far - to the design level - but
obviously, it's probably the simplest way to get what you want.
Very cool, the things one learns!
7:03 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Sep 5, 2014, at 21:00, "drlegendre ." <drlegendre at gmail.com> wrote:
So a GFI doesn't respond to currents flowing through the ground circuit,
but to current differentials in the hot & neutral circuits - is that
correct? If that's true, then it doesn't really matter what's going on in
the ground circuit - so long as the Ineutral < Ihot there's a fault
condition.. there's a current going somewhere it's not intended to flow, eh?
That's exactly it, and exactly the problem it's meant to
address.
- Dave
6 Sep
6 Sep
12:51 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Your statement made me think for a moment.. and it became clear that I must
not fully understand the function of GFCI hardware.
Now if a GFI can operate on an outlet with n/c to the 3rd prong (read: no
ground wire) that +must+ mean that the GFI can sense a situation where a
first current I is flowing in the hot lead (black) but it's not equal to a
second current I' that is flowing in the neutral (white).
YEs, that is exactly what they do. If you think about it, it's tbe most
sensible thing to do. Sensing the currenti n the (green) earth wire would
detact a leak via that wire, but current wil lonylflow there if (a) the
earhth wirie is earhted and ()b) the leakage aoccurs to some thign that
is conencted to the earth wire.
By detectign an imbalance in live nad neutral currents the GFI [1] will
trip if the leak occurs through some other path. Say if you accedientally
touch a live part. The current frols to warht not via the earth wire of
htt device, but as the live an neutral currents are now imbalanced a GFI
would trip, hopefully protectign you.
[1] We tend to call them RCD's (Residual Current Device). The old name
here was ELCB (Earth Leakage Circuit Breaker.
An example would be a radio that draws 500mA under normal conditions, where
500mA flows in both the hot & neutral. But if the radio falls in the
bathtub, now we might see a current of 750mA flowing in the hot, but only
500mA flowing in the neutral and an additional, anomalous 250mA flowing
"somewhere" - which in this case, would be through the water / human to the
cold-water pipe ground (via a metal tub, or metal drain hookup, etc).
So a GFI doesn't respond to currents flowing through the ground circuit,
but to current differentials in the hot & neutral circuits - is that
correct? If that's true, then it doesn't really matter what's going on in
the ground circuit - so long as the Ineutral < Ihot there's a fault
condition.. there's a current going somewhere it's not intended to flow, eh?
Exaactly.
Hwoever, I would still recoemnd having the earth (ground) wiring
conencted up). Firstly becasue if the GFI fials (and they can do) it's
another protection system. Secodnly, samll leakage currents which will
not trip the GFI can, under some circumstances cause enoguh voltage
differencebetween 2 devices that you will ahve problems with TTL level or
RS232 conenctions between them.
-tony
7 Sep
7 Sep
9:05 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Tony,
On Sat, Sep 6, 2014 at 2:51 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
YEs, that is exactly what they do. If you think about it, it's tbe most
sensible thing to do.
Not to put too fine a point on it, but I +did think+ about it - and as
such, arrived at the correct functional model as outlined above.. ;-)
Honestly, I'd never really given much thought to the behavior of GFCIs.. my
vague mental model was more-or-less based on detection of anomalous
currents flowing in the ground circuit. But of course, if you think about
it (...) that would only protect against one category of fault. Once Eric
stated that GFCIs can function on two-wire circuits, it was immediately
clear that my model needed to be discarded, which forced me to re-think
matters for a moment.
So yes, detecting current differentials wrt hot & neutral is really the
best (if not the only) method to achieve the desired aims.
6 Sep
6 Sep
12:43 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
At any rate, I don't think you need to worry about
90 microamps leakage.
Most US GFCIs don't trip until the leakage current is somewhere around
6 ma--or about 60 times what you're seeing.
I am not sure what the legally allowable leakage current (to pass a PAT
test) is in the UK, but personally, if the leakage resistance is gettign
close ot 1M Ohm I want ot know the reason why.
It may be OK, it may be part od the desing. Or it may be comething
breaking down which can only get worse.
An example. I havbe an HP13215 PSU here (for the 7900 disk drive) which
shows just over 1M of leakage form the mains input to chassis.
Disconnecvting wires shows that the transformer is fine (getting on for
100M OHms, the leak is i nthe mains fitler can. This is certainly a DC
leak, and even shows up usign a noraml DMM.
I've not had a chance to invetigate further. If this is a discharge
resistor in the mains filter (they were nto uncommon at opne time) to
discharge the fitler caps and prevent shock,s then fine. If it;s a
capacitor breakign down then not fine. I need to investigate before I use
the PSU seriously.
-tony
2:08 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Sep 6, 2014, at 3:43 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
I don?t know the limits in the US either, but I agree 100% with your sentiment. Wire
insulation and other insulation in transformers, when in good condition, should have
impedance in the hundreds of megaohms at least, if not higher. One megaohm indicates it?s
suffering serious decay. Either that, or it?s 80 years old and built using materials that
were both very low tech and very low quality (i.e., ?cheap junk?). Note that some of the
very best insulators have been known and in use for over a century, so age alone does not
excuse high leakage.
paul
At any rate, I
don't think you need to worry about 90 microamps leakage.
Most US GFCIs don't trip until the leakage current is somewhere around
6 ma--or about 60 times what you're seeing.
I am not sure what the legally allowable leakage current (to pass a PAT
test) is in the UK, but personally, if the leakage resistance is gettign
close ot 1M Ohm I want ot know the reason why.
7 Sep
7 Sep
12:17 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Sep 6, 2014, at 3:43 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
I don?t know the limits in the US either, but I agree 100% with your
sentiment. Wire insulation and other insulation in transformers, when
in good condition, should have impedance in the hundreds of megaohms at
least, if not higher. One megaohm indicates it?s suffering serious
FIWW, most,(in fact almost all) of the classic computer mains transformers I
have tested have had nice, high, insualtion resistances. When they start
getting coparable to the leakage between the terminals on my tester (as
has happened several times) I know there's nothing to worry about.
At any
rate, I don't think you need to worry about 90 microamps leakage.
Most US GFCIs don't trip until the leakage current is somewhere around
6 ma--or about 60 times what you're seeing.
I am not sure what the legally allowable leakage current (to pass a PAT
test) is in the UK, but personally, if the leakage resistance is gettign
close ot 1M Ohm I want ot know the reason why. decay. Either that, or it?s 80 years old and built
using materials that
were both very low tech and very low quality (i.e., ?cheap junk?). Note
Or it's very new and cheap junk. Seriously. I ahve had new, cheap,
transfoemrs with low insulation resistane readings. Probably just above
the requirment, so they are 'sagfe', but I am not going to trust them.
that some of the very best insulators have been known
and in use for
over a century, so age alone does not excuse high leakage.
Incidetnally IMHO while protective systems like safety earths (grounds)
and RCDs (GFIs) are undoubtedly a good thing (and of course I use them),
they are there to protect you if soemthign goes wrong. They are not a
substitute for good design and workmanship using the right materials.
-tony
6 Sep
6 Sep
12:37 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Chuck & All,
On Fri, Sep 5, 2014 at 4:23 PM, Chuck Guzis <cclist at sydex.com> wrote:
I think you should stop working on the Altair and sort out your workshop
wiring. Before you plug soemthing in with a serious leak and get
electrocuted.
Regardless, it doesn't answer the question about why the chassis isn't
grounded. The 8800 was most certainly equipped with a 3-conductor line
cord.
You'll have to look up a bit for the answer.
The chassis most certainly +does+ have a 3-wire cord, and it's properly
connected. Thing is, I live in a really old house (for the USA, anyway) and
it turns out that one of the circuits that's near my workbench doesn't
actually have a ground wire - and it turns out that's the circuit which was
being used to power the Variac which in turn powers the Altair.
I only discovered this issue last week, in the process of working on the
Altair, when I felt that tell-tale buzz on my fingertips as they happened
to lightly graze the chassis at one point. Same feel you get from a vintage
amp with a 2-wire cord and an AC line bypass to chassis.. the so-called
"Death Cap", in the lingo of some guitar doofuses who don't seem to grasp
the concept of impedances, and how little current that 50-100nF cap can
actually pass through the resistance of a human body at 60hz.
Well, 100nF on a 110V 60Hz supplywill pass over 4mA. That could be enough
to be dangerous under certain condtions. You certainly would not get me
to tocuh an unearthed chasssis connected to the live side of the mains
through a 100nF capacitor.
-tony
7 Sep
7 Sep
9:34 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Tony & All,
On Sat, Sep 6, 2014 at 2:37 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
I think you should stop working on the Altair and sort out your workshop
wiring. Before you plug soemthing in with a serious leak and get
electrocuted.
It is sorted.. I'm not using that circuit for my bench any longer. In fact,
it was never actually a bench circuit - I was using a different (more
spacious) table to deal with the Altair, and was powering the equipment on
that table from another outlet.
This house was built in the 1870s. The present 100A service was installed
sometime in the early 1980s, but apparently code didn't require updating of
all the outlets at that time (either that, or they just plain shirked it).
All of the "new" circuits are 3-wire, but there are still a few legacy
2-wire circuits in here - terminated in new-ish 3-wire outlets, of course.
9:52 a.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
In any event, I'll be out of town for a while. When I return, it will be
time to button-up the Altair project - hook up a power switch, finalize the
board / chassis grounding scheme, complete the lead dress & routing,
fabricate original-style expanded metal screens to cover the connector
slots in the case, install the fan, front panel and case, etc.
You know, all of the "fun & easy" stuff that doesn't require scopes,
probes, datasheets and hours of troubleshooting.. the i-dotting, t-crossing
detail work that really makes the job all proper and workmanlike, and sets
it apart from so many carelessly assembled kits and poorly-executed
"restorations".
At that time, I'll investigate the leakage problem further.
Incidentally, does anyone have +mechanical drawings+ for the metal screens
that would have originally covered the connector slots? And do we know
whether or not the fan hole also had a protective screen? I've never seen
any good photos of a factory-correct back panel - either inside, or
outside. Only one poor shot that semi-shows that a perforated / expanded
metal screen +was+ used over the slots. That info would be helpful for sure!
On Sun, Sep 7, 2014 at 11:34 AM, drlegendre . <drlegendre at gmail.com> wrote:
Tony & All,
On Sat, Sep 6, 2014 at 2:37 PM, Tony Duell <ard at p850ug1.demon.co.uk>
wrote:
I think you should stop working on the Altair and sort out your workshop
wiring. Before you plug soemthing in with a serious leak and get
electrocuted.
It is sorted.. I'm not using that circuit for my bench any longer. In
fact, it was never actually a bench circuit - I was using a different (more
spacious) table to deal with the Altair, and was powering the equipment on
that table from another outlet.
This house was built in the 1870s. The present 100A service was installed
sometime in the early 1980s, but apparently code didn't require updating of
all the outlets at that time (either that, or they just plain shirked it).
All of the "new" circuits are 3-wire, but there are still a few legacy
2-wire circuits in here - terminated in new-ish 3-wire outlets, of course.
12:38 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Tony & All,
On Sat, Sep 6, 2014 at 2:37 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
Well, that's oen form of 'sorted' I guess...
More seriosuly, I have a healthy respsect for the mains. I am not afraid
of it, I work with 230V (nearer 240V, actually) mains most days. But I
know it can also cauase enough current to flow through me to kill me [1],
so I don't give it the chance.
What I mean by that is that I do not accept anything 'dubiious'. Even
i I know about it, sombody else might make a mistake. In your position I
would sort out the wirign ASAP, make sure all socket outlets have groudn
wires, and so on.
[1] As I was taught many years ago 'It's the volts that jolts but the
mills [2] that kills'
[2] milliamps, of course.
Even woese than having no earth to a socket is the situation where a
numbero f ccoekt outlets ahve the earth pins all linked together but not
then conencted to ground. The reason is that if there is a leak on
anything plugged into one of said sockets, the metal cases of things
pluggedi nto the oterhs will become live. And yes I did once come acorss
such a situation. As soon as I pointed it out it got fixed -- ASAP.
-tony
I think you should stop working on the Altair and sort out your workshop
wiring. Before you plug soemthing in with a serious leak and get
electrocuted.
It is sorted.. I'm not using that circuit for my bench any longer. In fact,
4:36 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Sep 7, 2014, at 12:34 PM, drlegendre . <drlegendre at gmail.com> wrote:
...
sometime in the early 1980s, but apparently code didn't require updating of
all the outlets at that time (either that, or they just plain shirked it).
All of the "new" circuits are 3-wire, but there are still a few legacy
2-wire circuits in here - terminated in new-ish 3-wire outlets, of course.
?Of course? ? hm. Code allows existing 2-wire circuits to be kept, BUT you are then
required to use 2 prong outlets. Use of 3 prong outlets on a 2 wire branch is a code
violation. So the best fix is to install a ground wire, but failing that the answer is to
use the correct outlet.
paul
4:47 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Sun, Sep 7, 2014 at 5:36 PM, Paul Koning <paulkoning at comcast.net> wrote:
?Of course? ? hm. Code allows existing 2-wire
circuits to be kept, BUT you are
then required to use 2 prong outlets. Use of 3 prong outlets on a 2 wire branch
is a code violation.
Actually code allows use of 3-prong GFI outlets on a 2-wire (no ground) branch,
provided that they are marked as such.
9:59 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Yes, "of course" - else I'd not been able to plug-in the 3-wire outlet
strip that I was connected to.. =)
Don't worry yourselves.. the grounds will go where they need to go, as time
and physical ability allows.
On Sun, Sep 7, 2014 at 6:36 PM, Paul Koning <paulkoning at comcast.net> wrote:
On Sep 7, 2014, at 12:34 PM, drlegendre . <drlegendre at gmail.com> wrote:
...
sometime in the early 1980s, but apparently code didn't require updating
of
all the outlets at that time (either that, or
they just plain shirked
it).
All of the "new" circuits are 3-wire,
but there are still a few legacy
2-wire circuits in here - terminated in new-ish 3-wire outlets, of
course.
?Of course? ? hm. Code allows existing 2-wire circuits to be kept, BUT
you are then required to use 2 prong outlets. Use of 3 prong outlets on a
2 wire branch is a code violation. So the best fix is to install a ground
wire, but failing that the answer is to use the correct outlet.
paul
5 Sep
5 Sep
3:32 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
On Fri, Sep 5, 2014 at 3:28 PM, Paul Koning <paulkoning at comcast.net> wrote:
2 nF is what I get, too. That wouldn?t be stray capacitance in the
transformer. But it could be an EMI filter capacitor, if the PSU has such
things. A DC test would sort that out.
Arrrrggghhh!!!
I swear on my dead grandmother's eyes, there is NO EMI filter or bypass
cap, lol.
6 Sep
6 Sep
12:28 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
85uA at 11)V, say is a resistance/impedance of about 1.3MOhms. At 60Hz,
that would seem to correspond to the reactance of a 2 nF capacitor (check
this, I may have made a mistake in the calculation). That sounds high for
a 'stray' to me.
2 nF is what I get, too. That wouldn?t be stray capacitance in the
transformer. But it could be an EMI filter capacitor, if the PSU has
such things. A DC test would sort that out.
3 Sep
3 Sep
12:09 p.m.
New subject: Questions - Setting up a SRAM board in S-100 / Altair system?
Howdy,
On Tue, Sep 2, 2014 at 2:08 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
Yes, drawn as an OR with inverter bubbles at the inputs.
Whih does make sense.
Just noticed some errors in the CCS DRAM board schematic. Both U4
(74LS20)
and U5 (7400) are drawn as an OR gates. I'm
sure there's more..
I've not seen the schamtics, but are they drawn, perhaps, as OR gates
_with inverting circles on the inputs_? Rememebr that a positive logic
AND gate is a negative logic OR gate (De Morgan's lwa, essentially). That
is, if you have 2 active low signals (signals that are true when low/0),
and feed them into am AND gate like a 7408, then output, if considerd
also to be actiuve low, is true is either of the inputs is true
(translation : the output of an AND gate is 0 if either of the inputs is
0). So calling it an OR gate makes sense.
-tony
Hmm.. negative logic vs. positive logic.. that's a new one to me. Sure, I
get what you're saying, but at my current level it really seems like an
unnecessary complication / confusion. The data sheet calls out the 7408 as
"quad AND gate", and that's how it behaves, so that's how I expect a
7408
to be drawn.. as AND gates.
But it's only an AND gate usign the convention that an input voltage >2V
is a 1m etc.
PErsonally, i do not like the covnention of using the 'wrong' symbols and
adding inverting bubbles, but like you I can see the point .In my own
diagrams (whether design or reverse-engineered) I always use the normal
data sheet symbol. Others feel diffrently about this, and I certianly
have no problems redign a diagram that uses such symbols
As time goes on and experience grows, I'm sure the 'wisdom' of their
choices will become more evident. At the moment, it's a distraction.
So then, let's move on to the section on configuring the switches on the
board. Frankly, it appears not only confusing and just plain wrong, it also
appears to contradict itself. I think this is the stuff that Brent was
mentioning earlier - if you set those switches the way the doc indicates,
the memory gets mapped to the top-end of the 64K range, as opposed to the
bottom end. That one I verified. Also, the switches on the board are in
reverse order vs. the switch tables drawn in the manual.
Then there's the strange statement.. "closed=0 open=1", bottom of p.1-5.
Now that defies every convention known to man.. 0=false=open=off /
1=true=closed=on in my world.
I suspect this comes from the fact that it is much easier to pull a TTL
input high (make it a '1') that to pull it low (make it a '0').
If you want to pull a TLT input hight you cna use quite a large resisotor
--4.7k, for example -- between the input and Vcc. To make it low you need
a much lower reissotr, a fw hundred ohms at most. So if you are goign to
use a simple on/off swithc to drvie a TTL input it takes lt is bett to
conenct the switch between the input and grounf and to have the higher
value pull-up resisotr.
In that case, a closed switch makes the TTL input a logic 0 state.
I have often thought that a lot of TTL design would be easier if the
logic levels had been reversed, that is, if '1' nad been the state close
to ground. But anyway...
-tony
1 Sep
1 Sep
7:18 p.m.
On 2014-Sep-01, at 5:28 PM, drlegendre . wrote:
bar-over-<symbol> means "the complement of", generally read as
not-<symbol>.
e.g.:
bar over Q is not-Q.
No, not active high, it actually often means active low.
e.g.:
PWR is processor-write (write sig from processor)
bar over PWR == not-PWR
== not processor write
== active low processor write
== processor write is active when this line is low
My own personal standard for purposes of textual representation is to prefix the name of
an inverted signal with lowercase-n.
e.g. not-PWR --> nPWR
There are other standards, all of them with their own benefits and detriments.
Going backwards:
- U9 is the refresh address counter.
- The bus RFSH signal is gated through U7-pins8,9,10 to increment U9, but it is also
incremented through U16 (div-by-10), U6-pin9.
- U16 is clocked by bus phase-1 or phase-2. U16 appears to implement the
delay-between-refresh cycles.
It doesn't need an on-board oscillator because it's using the bus clock sigs
(phases).
2MHz from the bus divided by 10 via U16 = refresh cycles at a 200KHz rate.
200KHz divided by 128 or 256 in U9 gives a regeneration period in the ballpark of a
millisecond for each row, which is about right for the chips.
Usually when a board uses the RFSH signal, it uses the refresh address a Z80 is putting
out on the address bus rather than it's own counter.
I haven't examined it enough detail to be sure the onboard refresh is *entirely*
self-supporting, but it looks like it is.
You could try scoping U14-pins1,19. If the refresh circuitry is active there should be a
repetitious pulse there on the order of 200KHz, gating the refresh address onto the DRAM
chip address lines.
Thanks for the input again..
On Mon, Sep 1, 2014 at 6:21 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
To start in on
board-level debugging, one thing to check: if the board is
enabled and a valid address for the board is on the bus, then U4 pin 8
should be high.
Hey cool, that's the kind of info I need to keep me going. I'll take a
look
at that in a bit.. or, take a look at that bit in a while or something.
So here's a question or two. First off, how do you pronounce a letter
designation with a line over it - like the outputs of a flip-flop are Q and
(Q with overline). Do you say "Q high" or "Q prime".. "Q
complement" or
what? What about when a named signal such as CLOC or PWR has an overline?
Do you pronounce it "CLOC active high" or something?
(Does that line actually mean "active high"? - that's what I've
surmised..) Finally, on the CPU board, pin 49 supplies the CLOC
signal.. but it's
actually pins 25 & 24 that the DRAM card look to for +its+ clock signal.
Those pins are marked with what looks like a ?-1 and ?-2 (Greek Phi),
respectively. Is that actually a 'phi', and if so, what does it mean - what
are those signals, if not clock signals? And how do you pronounce them? It
could be a slashed-zero, too... "?".
(Generally Theta (?) is used to denote a phase /
angular relationship or
quantity. it looks kinda like phi, but it's not.)
Yes, it is phi, and is pronounced as phase-1, phase-2, etc.
Yes, it is derived from the physics/math angular relationship, as it generally refers to
repetitious (clock) signals with a phase (angular) displacement from each other.
For the bus, not-CLOC (pin 49) is the raw clock, two clock phases are derived from this,
put on pins 24 & 25.
I haven't
examined the schematic in enough detail to quite convince myself
for sure the board will work without the RFSH signal, but that would affect
the writing/retention.
I'm a bit confused.. all DRAMs need a refresh, and the doc for this board
is pretty explicit that it needs "the correct" (ugh!) phase of the clock
signal "on pins 24 & 25". Why would you think the board doesn't
require
such a signal, that it has its own on-board refresh hardware? FWIW, there's
no crystal on-board to control an osc. to that level of precision.
7:47 p.m.
Excellent, Brent. Thanks again, particularly on the misunderstood
symbology. Give me a while to digest all that.. I'm about out of time for
the night, maybe.
On Mon, Sep 1, 2014 at 9:18 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Sep-01, at 5:28 PM, drlegendre . wrote:
look
there's
Thanks for the input again..
On Mon, Sep 1, 2014 at 6:21 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
> To start in on board-level debugging, one
thing to check: if the board
is
enabled
and a valid address for the board is on the bus, then U4 pin 8
should be high.
Hey cool, that's the kind of info I need to keep me going. I'll take a
at that in a bit.. or, take a look at that bit in
a while or something.
So here's a question or two. First off, how do you pronounce a letter
designation with a line over it - like the outputs of a flip-flop are Q
and
(Q with overline). Do you say "Q high"
or "Q prime".. "Q complement" or
what? What about when a named signal such as CLOC or PWR has an overline?
Do you pronounce it "CLOC active high" or something?
(Does that line actually mean "active high"? - that's what I've
surmised..)
bar-over-<symbol> means "the complement of", generally read as
not-<symbol>.
e.g.:
bar over Q is not-Q.
No, not active high, it actually often means active low.
e.g.:
PWR is processor-write (write sig from processor)
bar over PWR == not-PWR
== not processor write
== active low processor write
== processor write is active when this
line is low
My own personal standard for purposes of textual representation is to
prefix the name of an inverted signal with lowercase-n.
e.g. not-PWR --> nPWR
There are other standards, all of them with their own benefits and
detriments.
Finally, on the CPU board, pin 49 supplies the
CLOC signal.. but it's
actually pins 25 & 24 that the DRAM card look to for +its+ clock signal.
Those pins are marked with what looks like a ?-1 and ?-2 (Greek Phi),
respectively. Is that actually a 'phi', and if so, what does it mean -
what
are those signals, if not clock signals? And how
do you pronounce them?
It
could be a slashed-zero, too... "?".
(Generally Theta (?) is used to denote a phase /
angular relationship or
quantity. it looks kinda like phi, but it's not.)
Yes, it is phi, and is pronounced as phase-1, phase-2, etc.
Yes, it is derived from the physics/math angular relationship, as it
generally refers to repetitious (clock) signals with a phase (angular)
displacement from each other.
For the bus, not-CLOC (pin 49) is the raw clock, two clock phases are
derived from this, put on pins 24 & 25.
> I haven't examined the schematic in
enough detail to quite convince
myself
> for sure the board will work without the RFSH
signal, but that would
affect
the
writing/retention.
I'm a bit confused.. all DRAMs need a refresh, and the doc for this board
is pretty explicit that it needs "the correct" (ugh!) phase of the clock
signal "on pins 24 & 25". Why would you think the board doesn't
require
such a signal, that it has its own on-board refresh hardware? FWIW, no crystal on-board to control an osc. to that
level of precision.
Going backwards:
- U9 is the refresh address counter.
- The bus RFSH signal is gated through U7-pins8,9,10 to increment
U9, but it is also incremented through U16 (div-by-10), U6-pin9.
- U16 is clocked by bus phase-1 or phase-2. U16 appears to
implement the delay-between-refresh cycles.
It doesn't need an on-board oscillator because it's using the bus clock
sigs (phases).
2MHz from the bus divided by 10 via U16 = refresh cycles at a 200KHz rate.
200KHz divided by 128 or 256 in U9 gives a regeneration period in the
ballpark of a millisecond for each row, which is about right for the chips.
Usually when a board uses the RFSH signal, it uses the refresh address a
Z80 is putting out on the address bus rather than it's own counter.
I haven't examined it enough detail to be sure the onboard refresh is
*entirely* self-supporting, but it looks like it is.
You could try scoping U14-pins1,19. If the refresh circuitry is active
there should be a repetitious pulse there on the order of 200KHz, gating
the refresh address onto the DRAM chip address lines.
2 Sep
2 Sep
11:16 a.m.
The 'new' SRAM board arrived today.. and while I don't want to count my
chickens, it seems that the machine has regained much of its sanity. The
BOARD LED is on, and the BANK LED comes on anytime I address a location
within the range of the card. So I can now DEP & EX memory locations with
very good repeat-ability; it's almost to the point that I'm willing to plug
in a little test code and see what comes out! I'd call this +GOOD NEWS+ !!
There are still bugs to work out.. A7 LED is stuck ON for one example.
But there's a more subtle issue afoot here, one that I've been suspecting
but haven't been able to confirm, in light of all the other strange
behavior (kind of a high noise floor, so to speak). But now it seems clear
there are a lot of contact issues between the mainboard and the plug-in
cards. Just slightly disturbing a card can cause all kinds of wacky
behavior, and sometimes it takes several RESETs to get it to come up in a
sane state.
(Sometimes the current paths get established, other times they don't - I'm
sure you know the drill.)
So what's the approved method for cleaning & enhancing the contact on those
old S-100 card-edge connectors? I've been cleaning the card edges with
Q-tips & isopropyl - using the cotton to mop-up most of the dirt, then
breaking off the end and using the cardboard shaft to give it a bit of
burnish. But how & what to get down inside the board connectors?
Are there any contact enhancers, like Pro-Gold or Cramolin, etc. that are
safe & suggested for use in this situation? Unreliable card connections are
simply not tolerable..
Anyway, now I need to understand why the block-assignment DIP switches
behave the opposite of what's shown in the document. I believe Brent
mentioned something about this, sometime back.. but as it sits, the groups
are being assigned to F000-FFFF rather than 0000-0FFF (checkout begins with
all blocks assigned to the same starting address, 0000 - this effectively
'buries' groups B, C and D beneath group A, making the board appear as if
it's only 4K.)
On Mon, Sep 1, 2014 at 9:47 PM, drlegendre . <drlegendre at gmail.com> wrote:
Excellent, Brent. Thanks again, particularly on the
misunderstood
symbology. Give me a while to digest all that.. I'm about out of time for
the night, maybe.
On Mon, Sep 1, 2014 at 9:18 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
On 2014-Sep-01, at 5:28 PM, drlegendre . wrote:
look
board
Thanks for the input again..
On Mon, Sep 1, 2014 at 6:21 PM, Brent Hilpert <hilpert at cs.ubc.ca>
wrote:
> To start in on board-level debugging, one
thing to check: if the board
is
enabled
and a valid address for the board is on the bus, then U4 pin 8
should be high.
Hey cool, that's the kind of info I need to keep me going. I'll take a
at that in a bit.. or, take a look at that bit in
a while or something.
So here's a question or two. First off, how do you pronounce a letter
designation with a line over it - like the outputs of a flip-flop are Q
and
(Q with overline). Do you say "Q high"
or "Q prime".. "Q complement" or
what? What about when a named signal such as CLOC or PWR has an
overline?
Do you pronounce it "CLOC active high"
or something?
(Does that line actually mean "active high"? - that's what I've
surmised..)
bar-over-<symbol> means "the complement of", generally read as
not-<symbol>.
e.g.:
bar over Q is not-Q.
No, not active high, it actually often means active low.
e.g.:
PWR is processor-write (write sig from processor)
bar over PWR == not-PWR
== not processor write
== active low processor write
== processor write is active when this
line is low
My own personal standard for purposes of textual representation is to
prefix the name of an inverted signal with lowercase-n.
e.g. not-PWR --> nPWR
There are other standards, all of them with their own benefits and
detriments.
Finally, on the CPU board, pin 49 supplies the
CLOC signal.. but it's
actually pins 25 & 24 that the DRAM card look to for +its+ clock signal.
Those pins are marked with what looks like a ?-1 and ?-2 (Greek Phi),
respectively. Is that actually a 'phi', and if so, what does it mean -
what
are those signals, if not clock signals? And how
do you pronounce them?
It
could be a slashed-zero, too... "?".
(Generally Theta (?) is used to denote a phase /
angular relationship or
quantity. it looks kinda like phi, but it's not.)
Yes, it is phi, and is pronounced as phase-1, phase-2, etc.
Yes, it is derived from the physics/math angular relationship, as it
generally refers to repetitious (clock) signals with a phase (angular)
displacement from each other.
For the bus, not-CLOC (pin 49) is the raw clock, two clock phases are
derived from this, put on pins 24 & 25.
> I haven't examined the schematic in
enough detail to quite convince
myself
> for sure the board will work without the RFSH
signal, but that would
affect
the
writing/retention.
I'm a bit confused.. all DRAMs need a refresh, and the doc for this is pretty explicit that it needs "the
correct" (ugh!) phase of the clock
signal "on pins 24 & 25". Why would you think the board doesn't
require
such a signal, that it has its own on-board refresh hardware? FWIW,
there's
no crystal on-board to control an osc. to that
level of precision.
Going backwards:
- U9 is the refresh address counter.
- The bus RFSH signal is gated through U7-pins8,9,10 to increment
U9, but it is also incremented through U16 (div-by-10), U6-pin9.
- U16 is clocked by bus phase-1 or phase-2. U16 appears to
implement the delay-between-refresh cycles.
It doesn't need an on-board oscillator because it's using the bus clock
sigs (phases).
2MHz from the bus divided by 10 via U16 = refresh cycles at a 200KHz rate.
200KHz divided by 128 or 256 in U9 gives a regeneration period in the
ballpark of a millisecond for each row, which is about right for the chips.
Usually when a board uses the RFSH signal, it uses the refresh address a
Z80 is putting out on the address bus rather than it's own counter.
I haven't examined it enough detail to be sure the onboard refresh is
*entirely* self-supporting, but it looks like it is.
You could try scoping U14-pins1,19. If the refresh circuitry is active
there should be a repetitious pulse there on the order of 200KHz, gating
the refresh address onto the DRAM chip address lines.
4 Sep
4 Sep
6:42 p.m.
On Mon, 1 Sep 2014, drlegendre . wrote:
Being pretty new to all this, I can tell you that
reading datasheets and
devising tests for 74XX series ICs is a very good way to learn your way
around the world of digital logic - it's actually been a very helpful
series of learning exercises.. far better than listening to a lecture or
reading a textbook. Man am I glad I picked up & repaired that proto /
trainer chassis.. dang thing has really been coming in handy!
Do you have any idea who made/sold it? It's pretty similar in concept to
a Heathkit ET-3200, but way more versatile. Based on the workmanship
(the occasional lack of..) I think it was built by a student, probably
as part of a tech school course, or maybe a mail correspondence course?
Either way, it's a decent piece of equipment and it works great after
going through it -
https://nerp.net/~legendre/altair/photos/proto-trainer.jpg
I don't know which model you have, but that trainer was made by RSR
Electronics. Do you have any photos of the boards inside the trainer?
I have a similar but slight newer RSR Electronics trainer in my active
repair pile right now. As you suspected, these were commonly sold as kits
and were often poorly assembled. The one I have will need to be completely
resoldered, and all the toggle switches will be replaced (the assembler
melted them when soldering and several don't work at all). It also has
failed/popped filter caps in its DC power supply and a cooked pc board
(melted black goo) where the TO-220 transistor is mounted to the board
that the rotary switches are also soldered to. I found an inexpensive
Aavid TO-220 heatsink that fits the board layout and silkscreen perfectly
that I plan to install. One major gripe I have with the design is a lack
of a Molex connector for the power transformer which made removing the
main board extremely difficult (I finally snipped the wires off at the
board). The board was clearly designed for a header, but like the TO-220
heatsink, they were being cheap and left that out of the kit. I've already
sourced a header/connector though and will be fixing that when I redo the
rest of it. If you decide to replace the electrolytics in one of these, be
aware of the lone bipolar/non-polarized cap used in the function generator
circuit. If your boards are the same as those in the trainer I have here,
I have a repair parts list that also includes all of the electrolytics.
5 Sep
5 Sep
8:17 a.m.
On Thu, Sep 4, 2014 at 8:42 PM, Tothwolf <tothwolf at concentric.net> wrote:
I don't know which model you have, but that trainer was made by RSR
Electronics. Do you have any photos of the boards inside the trainer?
Ah.. RSR Electronics. Excellent, now at least I have a manufacturer's name
to work with.
I have a similar but slight newer RSR Electronics
trainer in my active
repair pile right now. As you suspected, these were commonly sold as kits
and were often poorly assembled. The one I have will need to be completely
resoldered, and all the toggle switches will be replaced (the assembler
melted them when soldering and several don't work at all).
It sounds like my kit was in slightly more capable hands than yours. In
fact, it looks as if some of the boards may have been factory built..
though there were several bad joints here & there. I did have to replace
several switches, two in the 'logic' array and one of the pulsers. The
unit didn't see a lot of use, so as in your case, it was most likely a
matter of damage during assembly.
One switch was actually working fine, but had a very odd feel to it.. there
was a secondary 'click' in there, sort of like the feel of a disconnector
resetting inside the trigger group of an autoloading rifle, when you
release the trigger after a shot. Turns out that one side of the switch
body was broke clean off, and it was held (very) loosely in place with
black tape.. and it was a part that actually held one of the fixed
contacts! How in the heck that was continuing to work is a question above
my pay grade, lol.
It also has failed/popped filter caps in its DC power supply and a cooked
pc board (melted black goo) where the TO-220
transistor is mounted to the
board that the rotary switches are also soldered to. I found an inexpensive
Aavid TO-220 heatsink that fits the board layout and silkscreen perfectly
that I plan to install. One major gripe I have with the design is a lack of
a Molex connector for the power transformer which made removing the main
board extremely difficult (I finally snipped the wires off at the board).
The board was clearly designed for a header, but like the TO-220 heatsink,
they were being cheap and left that out of the kit. I've already sourced a
header/connector though and will be fixing that when I redo the rest of it.
If you decide to replace the electrolytics in one of these, be aware of the
lone bipolar/non-polarized cap used in the function generator circuit. If
your boards are the same as those in the trainer I have here, I have a
repair parts list that also includes all of the electrolytics.
Again, mine hadn't suffered the same ugly fate as yours.. in fact, I don't
even recall if I rebuilt the PSU or not. It may have just checked-out OK on
the scope. Same for the generator / clock section - I didn't have to mess
with it, at least not so far. I'll have to look at the issue you mention
wrt the lack of plug-header on the power transformer, but they did use
cables & header connectors to link the various boards & modules together,
so maybe I got lucky in that department.
When I find the time, I'll take some photos of the innards and post them to
my shell. Don't suppose you've come across any schematics or other docs for
these RSR devices? Any sense if they were supplied - as I'd guessed - as
part of a tech school or correspondence course?
10 Sep
10 Sep
1:21 a.m.
On Fri, 5 Sep 2014, drlegendre . wrote:
Check your filter caps anyway, even the small ones. The one I have is
newer than yours, so if it is an age factor, the caps in yours may have
issues as well. It could also be that the trainer I have here has a lot
more hours on it. They certainly didn't use high quality caps in the one I
have. The replacements I obtained will probably outlast the trainer
itself.
On Thu, Sep 4, 2014 at 8:42 PM, Tothwolf <tothwolf
at concentric.net> wrote:
I don't know about the model you have, but it was possible to buy fully
assembled units for the later models (at a much higher cost of course).
I don't know which model you have, but that
trainer was made by RSR
Electronics. Do you have any photos of the boards inside the trainer?
Ah.. RSR Electronics. Excellent, now at least I have a manufacturer's
name to work with.
I have a similar but slightly newer RSR
Electronics trainer in my
active repair pile right now. As you suspected, these were commonly
sold as kits and were often poorly assembled. The one I have will need
to be completely resoldered, and all the toggle switches will be
replaced (the assembler melted them when soldering and several don't
work at all).
It sounds like my kit was in slightly more capable hands than yours. In
fact, it looks as if some of the boards may have been factory built..
though there were several bad joints here & there. I did have to replace
several switches, two in the 'logic' array and one of the pulsers. The
unit didn't see a lot of use, so as in your case, it was most likely a
matter of damage during assembly. One switch was actually working fine, but had a very
odd feel to it..
there was a secondary 'click' in there, sort of like the feel of a
disconnector resetting inside the trigger group of an autoloading rifle,
when you release the trigger after a shot. Turns out that one side of
the switch body was broke clean off, and it was held (very) loosely in
place with black tape.. and it was a part that actually held one of the
fixed contacts! How in the heck that was continuing to work is a
question above my pay grade, lol.
At least two of the toggle switches in this one felt weird too. They take
a lot of extra force to switch. I'm sure I'd just find displaced contacts
in them if I were to disassemble them. The originals are very cheap import
parts anyway and the replacements I got are of much better quality. I've
also decided to replace the lighted rocker power switch too, but I just
can't decide if I should use a red or green switch (I have both in my
spare parts bins).
It also has
failed/popped filter caps in its DC power supply and a
cooked pc board (melted black goo) where the TO-220 transistor is
mounted to the board that the rotary switches are also soldered to. I
found an inexpensive Aavid TO-220 heatsink that fits the board layout
and silkscreen perfectly that I plan to install. One major gripe I have
with the design is a lack of a Molex connector for the power
transformer which made removing the main board extremely difficult (I
finally snipped the wires off at the board). The board was clearly
designed for a header, but like the TO-220 heatsink, they were being
cheap and left that out of the kit. I've already sourced a
header/connector though and will be fixing that when I redo the rest of
it. If you decide to replace the electrolytics in one of these, be
aware of the lone bipolar/non-polarized cap used in the function
generator circuit. If your boards are the same as those in the trainer
I have here, I have a repair parts list that also includes all of the
electrolytics.
Again, mine hadn't suffered the same ugly fate as yours.. in fact, I
don't even recall if I rebuilt the PSU or not. It may have just
checked-out OK on the scope. Same for the generator / clock section - I
didn't have to mess with it, at least not so far. I'll have to look at
the issue you mention wrt the lack of plug-header on the power
transformer, but they did use cables & header connectors to link the
various boards & modules together, so maybe I got lucky in that
department. When I find the time, I'll take some photos of the
innards and post them
to my shell. Don't suppose you've come across any schematics or other
docs for these RSR devices? Any sense if they were supplied - as I'd
guessed - as part of a tech school or correspondence course?
I have the assembly manuals and schematics for the model I have, but it
looks like it is very different from yours. They did include assembly
manuals and schematics with these trainers. Maybe RSR Electronics can
supply you with a copy of the assembly manuals for the model you have? At
the very least, hopefully they can tell you which model that is. These
trainers seem to be specified in some college electronics courses, but I
assume a student would have to purchase it themselves.
3538
days inactive
3550
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82 comments
10 participants
participants (10)
-
ard＠p850ug1.demon.co.uk -
bfranchuk＠jetnet.ab.ca -
cclist＠sydex.com -
cisin＠xenosoft.com -
drlegendre＠gmail.com -
fraveydank＠gmail.com -
hilpert＠cs.ubc.ca -
paulkoning＠comcast.net -
spacewar＠gmail.com -
tothwolf＠concentric.net