On Thu, Apr 25, 2013 at 2:40 PM, David Riley <fraveydank at gmail.com> wrote:
In any case, you should be able to fit the 360/30 FPGA
on the DE0, though you'll
have to create the project file and do the pin assignments yourself. You'll
also have to hack out any Xilinx-specific things in the VHDL if there are any,
which is usually just PLLs and block RAMs in most smaller projects (there are
other things that might be lurking, but they'd be unlikely in a project this
size). I don't know about the /65, though; that's on a much bigger FPGA that
has 110K equivalent LEs, and it uses PCI Express to communicate with the host PC
to run as the channel. It doesn't have sizing info, but that project would
definitely need significant mods to work with smaller boards. It might be a fun
(if somewhat advanced) project to port it to work on the Zynq, since the built-
in ARM would provide the functionality of the channel emulator quite nicely.
No guarantees on whether the 360/65 part of it would fit in the FPGA, though,
since there's no sizing info provided on the page (you could always try to
download and build it, though the free software won't build for a Virtex5 that
big; if you're really curious, I could build it with mine, since I have access
to the full suite).
That /65 is the one I'm creating. It's not quite finished yet, so I'd
stick with the /30 project which is known to run well.I don't expect
to be able to work on the /65 for a while, I'm in the process of
moving to a new home (with a lot more space for my hobbies).
Camiel