on FPGA simulation

Chuck wrote: Mouse wrote: Chuck's statement is a generalization, and of course all generalizations are false. It is possible to implement entirely asynchronous logic in an FPGA. I've done modest amounts of it. Xilinx says not to do it, primarily because their tools are really designed for it. The simulator and the static timing analyzer aren't good at dealing with asynchronous logic. The basic logic element in a Xilinx FPGA (and Altera are similar) has a LUT and a D flip-flop. The LUT is essentially a static RAM with four inputs (six in newer parts). The static RAM is specially designed to be glitchless when changing between two addresses that contain the same data, which allows it to behave as a normal logic gate when suitably programmed. The output of the LUT can either be used directly as the output of the logic element, or it can go into the D flip-flop. There are dedicated low-skew clock nets that feed the clock inputs of the D flip-flops. It is possible to feed the clock inputs from other signals, but not recommended. You can build your own S-R flip-flops out of gates implemented by LUTs. They work fine. If you absolutely *had* to take an existing asynchronous logic design and put it into an FPGA, and were willing to spend enough time on it, it can be made to work. In most cases, though, it is easier to redesign a system to operate synchronously, and then the FPGA tools are a lot more useful. Note that everything in the FPGA doesn't have to operate on the same clock. You can have multiple clock domains. However, then you have to be very careful with signals that cross clock domains. (That's true whether you use FPGAs or not.) It's generally best to minimize the number of independent clock domains as much as possible. Often there are things that at first glance would appear to need their own clock domain, but upon more careful study can be merged into another existing clock domain. Eric