on FPGA simulation

I wrote: Al Kossow wrote: I don't know about "better", but a key observation is that if you are transferring an n-bit data word between two clock domains, and use full handshaking (request/acknowledge) between the domains, and guarantee that the data from the source clock domain meets the setup time of the destination clock domain, then you only need the dual-rank synchronizers for the handshake signals and not the data. The synchronization in that case can be further simplified, i.e., you could use Rob Weinstein's "flancter" circuit: http://www.floobydust.com/flancter/Flancter_App_Note.pdf In many cases people use FIFOs for passing data between clock domains. It is *very* tricky to design your own asynchronous FIFO correctly, so it is often a good idea to use a FIFO macro supplied by your FPGA/CPLD vendor or EDA tools vendor. In fact, it is so tricky that even the vendors don't always get it right; Xilinx had some pretty serious errata for the hard FIFO logic they provided with their blockrams in some FPGA families. What I've done when I don't need pipelining is to build a one-word FIFO by using a single register and a flancter. Eric