26 Apr
2013
26 Apr
'13
9:45 a.m.
I don't
get your objection or what you see as an alternative to
modern FPGA vendors. FPGA hardware is well documented by all 4
major vendors at a cell, routing, and overall architecture level.
Mouse's
objection is based on the fact that they don't document the
functions of the configuration bitstream, without which you cannot
write your own synthesis software. > Pick up a family handbook from one of them and I
think you'll be
> shocked at just how much gory detail is actually in there - detailed
> almost down to a gate level. HDLs isolate you from having to deal
> with manually connecting gate A to gate B times thousands of nets in
> a relatively portable way.
I'm not against use of HDLs. I'm against _having to_ use HDLs. I'm
against having to use their choice of HDL. I'm _especially_ against
having to use their choice of compiler - which, as I noted a message or
two ago, probably won't run on either the OS or the CPU architecture I
want to run it on even if I were willing to run it.
Tools from
Xilinx, Altera, Lattice, and MicroSemi run on Linux as
well as Windows.
Mouse does not run Linux or Windows or x86 processors, to my knowledge.
Wrong. :( I do have and run some x86 machines, because those are what
other people are throwing out. I don't like them; I use them in places
where I am mostly isolated from them, such as backup server and house
routers; my screen-and-keyboard machines are SPARCstation 20s. Most of
my other architectures (68k, MIPS, ARM, PowerPC, Alpha) I have/run in
order to help keep my code CPU-portable. Two others have idiosyncratic
bases: VAX for the emotional attachments I have to it and Super-H
because the one I have has interesting harware integrated with it which
I want to play with.
Xilinx and Altera both used to run on Solaris and
HP-UX for Sparc and
HP-PA, respectively, but those were discontinued many years ago. For
modern FPGAs, you really need to be running pretty beefy, modern iron
to compile in any sort of reasonable timeframe.
Why? I can't see this as anything but the fault of the compiler.
My 8-core Xeon with 8 GB of RAM takes 45 minutes to
compile even a
medium-sized Arria II (Altera's mid-level FPGA) that's half-full, so
I don't think a SparcStation 20 would be an ideal candidate for
running the exhaustive search algorithms necessary for building
modern devices,
"Necessary"? Or "necessary to get high utilization percentages" or
some such? That is, is that exhaustive search necessary for
correctness or is it akin to optimization in a C compiler?
I suspect there are much cheaper algorithms that would get most of the
way there, wherever "there" is - but I can't experiment with that
either because of the vendors' draconian IP stupidity.
but if you were able to write your own generation
software, you could
at least route it yourself (with all the hazards that entails).
If. Exactly.
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