6 Feb
2012
6 Feb
'12
12:53 p.m.
On 06/02/2012 12:55, David Riley wrote:
On Feb 6, 2012, at 4:44 AM, Eric Smith wrote:
The end effect is reduced gain, sometimes accompanied by lower fmax.
Nowadays a factor of about two in hfe, but in years gone by it wasn't
unusual to see apparently-complimentary transistors with more than a
factor of ten difference.
--
Pete Peter Turnbull
Network Manager
University of York
On 02/05/2012 10:31 PM, Mouse wrote:
Nor am I an expert, but that's pretty much it. In CMOS ICs, the typical
practice is to double the channel width of the P channel to compensate for
the difference. This roughly equalizes the current of the two halves, but
the capacitance for the P transistor's gate is doubled because the gate
area is doubled. I don't recall how it affects bipolar devices, though I
imagine it's the same. But now I'm curious. What sort of performance
degradation does PNP exhibit? Slower switching? Higher power dissipation? And what's
the underlying difference behind it, do you know?
If I recall correctly (and
I'm no expert on solid-state physics, so I could easily be wrong), the difference
comes about because electron mobility in silicon is about three times the hole mobility.
Wikipedia says Si at 300K has electron mobility of 1400 cm^2/V*s, vs. hole mobility of 450
cm^2/V*s.