3 Oct
2019
3 Oct
'19
9:39 a.m.
On 10/3/19 9:01 AM, Noel Chiappa via cctalk wrote:
The PDP-6 and KA10 (basically a re-implementation of
the PDP-6 architecture)
both had cheapo versions where addresses 0-15 were in main memory, but also
had an option for real registers, e.g. in the PDP-6: "The Type 162 Fast
Memory Module contains 16 words with a 0.4 usecond cycle." The KA10 has
a similar "fast memory option".
A bit more contemporary example might be the low-end PIC
microcontrollers (e.g. the 12F series). Harvard architecture (14 bit
instructions, 8 bit data), but data is variously described as
"registers" (when used an instruction operand) or "memory" when
addressed indirectly. That is, the 64 bytes of SRAM can be referred to
as either a memory location or as a register operand.
This isn't unusual--the original STAR-100 had 256 64-bit registers that
could be addressed as register storage or as the first 256 words of
memory. Eventually, this capability was disabled (the so-called "Rev.
R" ECO) because of conflicts in usage.
--Chuck