3 Oct
2019
3 Oct
'19
9:01 a.m.
From: Paul Koning
Some early machines, the PDP-6 I believe is an
example, have
"registers" in the ISA but they actually correspond to specific parts
of main memory.
The PDP-6 and KA10 (basically a re-implementation of the PDP-6 architecture)
both had cheapo versions where addresses 0-15 were in main memory, but also
had an option for real registers, e.g. in the PDP-6: "The Type 162 Fast
Memory Module contains 16 words with a 0.4 usecond cycle." The KA10 has
a similar "fast memory option".
Noel
3 Oct
3 Oct
9:39 a.m.
On 10/3/19 9:01 AM, Noel Chiappa via cctalk wrote:
The PDP-6 and KA10 (basically a re-implementation of
the PDP-6 architecture)
both had cheapo versions where addresses 0-15 were in main memory, but also
had an option for real registers, e.g. in the PDP-6: "The Type 162 Fast
Memory Module contains 16 words with a 0.4 usecond cycle." The KA10 has
a similar "fast memory option".
A bit more contemporary example might be the low-end PIC
microcontrollers (e.g. the 12F series). Harvard architecture (14 bit
instructions, 8 bit data), but data is variously described as
"registers" (when used an instruction operand) or "memory" when
addressed indirectly. That is, the 64 bytes of SRAM can be referred to
as either a memory location or as a register operand.
This isn't unusual--the original STAR-100 had 256 64-bit registers that
could be addressed as register storage or as the first 256 words of
memory. Eventually, this capability was disabled (the so-called "Rev.
R" ECO) because of conflicts in usage.
--Chuck
10:26 a.m.
On Oct 3, 2019, at 12:39 PM, Chuck Guzis via cctalk
<cctalk at classiccmp.org> wrote:
On 10/3/19 9:01 AM, Noel Chiappa via cctalk wrote:
Then again, the PDP-10 has that "two ways to refer to it" as well. In that
case, you do have dedicated register logic, and what happens is that memory addresses 0-15
are instead redirected to the register array. The same applies to the EL-X8. The way you
can address things doesn't necessarily tell you what sort of storage mechanism is used
for it.
paul
The PDP-6 and KA10 (basically a re-implementation
of the PDP-6 architecture)
both had cheapo versions where addresses 0-15 were in main memory, but also
had an option for real registers, e.g. in the PDP-6: "The Type 162 Fast
Memory Module contains 16 words with a 0.4 usecond cycle." The KA10 has
a similar "fast memory option".
A bit more contemporary example might be the low-end PIC
microcontrollers (e.g. the 12F series). Harvard architecture (14 bit
instructions, 8 bit data), but data is variously described as
"registers" (when used an instruction operand) or "memory" when
addressed indirectly. That is, the 64 bytes of SRAM can be referred to
as either a memory location or as a register operand. 
11:04 a.m.
On Oct 3, 2019, at 10:26 AM, Paul Koning via cctalk
<cctalk at classiccmp.org> wrote:
So does the PDP-11. The 8 registers are mapped to the top 8 words of memory so you can do
some quite interesting things. It is also possible to run a (small) program in only the
registers (e.g. no memory at all).
TTFN - Guy
On Oct 3, 2019, at 12:39 PM, Chuck Guzis via
cctalk <cctalk at classiccmp.org> wrote:
On 10/3/19 9:01 AM, Noel Chiappa via cctalk wrote:
Then again, the PDP-10 has that "two ways to refer to it" as well. In that
case, you do have dedicated register logic, and what happens is that memory addresses 0-15
are instead redirected to the register array. The same applies to the EL-X8. The way you
can address things doesn't necessarily tell you what sort of storage mechanism is used
for it.
The PDP-6 and KA10 (basically a re-implementation
of the PDP-6 architecture)
both had cheapo versions where addresses 0-15 were in main memory, but also
had an option for real registers, e.g. in the PDP-6: "The Type 162 Fast
Memory Module contains 16 words with a 0.4 usecond cycle." The KA10 has
a similar "fast memory option".
A bit more contemporary example might be the low-end PIC
microcontrollers (e.g. the 12F series). Harvard architecture (14 bit
instructions, 8 bit data), but data is variously described as
"registers" (when used an instruction operand) or "memory" when
addressed indirectly. That is, the 64 bytes of SRAM can be referred to
as either a memory location or as a register operand. 
4 Oct
4 Oct
12:56 p.m.
On Thu, Oct 3, 2019 at 12:04 PM Guy Sotomayor Jr via cctalk <
cctalk at classiccmp.org> wrote:
So does the PDP-11. The 8 registers are mapped to the
top 8 words of
memory so you can do some quite interesting things. It is also possible to
run a (small) program in only the registers (e.g. no memory at all).
That's not an actual PDP-11 architectural feature, and it only works on the
KD-11B CPU (PDP-11/05 and 11/10). No other models can execute code from the
general purpose registers, or access the GPRs via a memory address. When an
instruction word is fetched from a GPR, the PC is only incremented by one,
because the 16-bit registers are at consecutive addresses, rather than
multiples of two as one would expect. The GPRs are not byte-addressable.
On all other Unibus PDP-11 processors made from TTL (i.e., not based on the
F11 or J11), the general-purpose registers can be accessed at the same
addresses from the console, but NOT from software.
Code can be executed from the MMU PAR registers on processors with 22-bit
addressing (11/23, 11/24, 11/44, 11/70, and J-11 based systems). These are
word registers at word addresses, so they don't have the increment-by-one
hack of the 11/05 executing from GPRs.
15 Oct
15 Oct
5:25 p.m.
On 10/3/2019 1:04 PM, Guy Sotomayor Jr via cctalk wrote:
FYI, not ALL PDP-11 implementations can do this. In particular, the J11
(used in PDP-11/73 and others) does not map the registers into memory
locations. I suspect, but have not verified, that any PDP-11 processor
with multiple register sets (e.g., one for user one for kernel, etc.)
are likely to behave this way.
(One on one reply since the message was quite old.)
JRJ
On Oct 3, 2019, at 10:26 AM, Paul Koning via
cctalk <cctalk at classiccmp.org> wrote:
So does the PDP-11. The 8 registers are mapped to the top 8 words of memory so you can
do some quite interesting things. It is also possible to run a (small) program in only
the registers (e.g. no memory at all).
TTFN - Guy
On Oct 3, 2019, at 12:39 PM, Chuck Guzis via
cctalk <cctalk at classiccmp.org> wrote:
On 10/3/19 9:01 AM, Noel Chiappa via cctalk wrote:
Then again, the PDP-10 has that "two ways to refer to it" as well. In that
case, you do have dedicated register logic, and what happens is that memory addresses 0-15
are instead redirected to the register array. The same applies to the EL-X8. The way you
can address things doesn't necessarily tell you what sort of storage mechanism is used
for it.
The PDP-6 and KA10 (basically a re-implementation
of the PDP-6 architecture)
both had cheapo versions where addresses 0-15 were in main memory, but also
had an option for real registers, e.g. in the PDP-6: "The Type 162 Fast
Memory Module contains 16 words with a 0.4 usecond cycle." The KA10 has
a similar "fast memory option".
A bit more contemporary example might be the low-end PIC
microcontrollers (e.g. the 12F series). Harvard architecture (14 bit
instructions, 8 bit data), but data is variously described as
"registers" (when used an instruction operand) or "memory" when
addressed indirectly. That is, the 64 bytes of SRAM can be referred to
as either a memory location or as a register operand. 
3 Oct
3 Oct
10:15 a.m.
On 10/3/2019 10:01 AM, Noel Chiappa via cctalk wrote:
The PDP-5 how soon theyy forget. The PC was in core memory for sure.
Not sure about the AC how ever.
The IBM 1130 had the index registers in Core at something like 1,2,3.
Today Fast memory is .4 ps. I wonder how the old machines
would compare with today's wonder CPU's assuming the same transistor
speeds.Ben.
From: Paul
Koning
Some early machines, the PDP-6 I believe is an
example, have
"registers" in the ISA but they actually correspond to specific parts
of main memory.
The PDP-6 and KA10 (basically a re-implementation of the PDP-6 architecture)
both had cheapo versions where addresses 0-15 were in main memory, but also
had an option for real registers, e.g. in the PDP-6: "The Type 162 Fast
Memory Module contains 16 words with a 0.4 usecond cycle." The KA10 has
a similar "fast memory option".
Noel 
5:15 p.m.
Noel wrote:
The PDP-6 and KA10 (basically a re-implementation of
the PDP-6 architecture)
both had cheapo versions where addresses 0-15 were in main memory, but also
had an option for real registers, e.g. in the PDP-6: "The Type 162 Fast
Memory Module contains 16 words with a 0.4 usecond cycle." The KA10 has
a similar "fast memory option".
http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-HMAA-D%20…
p 1-1 (pdf pg 13) says the CPU options were:
KE10 Extended Order Code (byte instructions)
KT10 Memory Protection and Relocation
KT10A Double Memory Protection and Relocation
KM10 Fast Registers
Elsewhere I have the note the the fast registers had 0.21 microsecond
access time.
1677
days inactive
1690
days old
7 comments
8 participants
participants (8)
-
bfranchuk＠jetnet.ab.ca -
cclist＠sydex.com -
cube1＠charter.net -
ggs＠shiresoft.com -
jnc＠mercury.lcs.mit.edu -
paulkoning＠comcast.net -
phil＠ultimate.com -
spacewar＠gmail.com