1 Sep
2014
1 Sep
'14
6:06 p.m.
Sorry for the trickle, here, but I'm making progress and need to keep
things rolling.
So OK, I think I understand how the board enable/disable circuits work, now
that Brent tipped me off to U4. The output of U4 runs to one input of the
3-input NAND at U3. PHANTOM also comes in on U3, as does another signal
from the output of U7 I don't know. Point is, so
long as all of these 3
remain high, the output of U3 remains low. If any of the 3 go
low, output
of U3 goes high.
The output of U3 ties to the (overlined) OE (output enable?) of U20.. which
is a tri-state device. So if that input were to go high, then the outputs
of U20 all go high-Z and effectively cut-off lines DI0-DI7 to the RAM
matrix. I think DI=Data In, right? So in other words, if any of the 3
inputs to U3 goes low, the DI0-DI7 lines go high-Z and cutoff from the
buss..
Did I get that right?
On Mon, Sep 1, 2014 at 7:41 PM, drlegendre . <drlegendre at gmail.com> wrote:
Just noticed some errors in the CCS DRAM board
schematic. Both U4 (74LS20)
and U5 (7400) are drawn as an OR gates. I'm sure there's more..
On Mon, Sep 1, 2014 at 7:28 PM, drlegendre . <drlegendre at gmail.com> wrote:
Thanks for the input again..
On Mon, Sep 1, 2014 at 6:21 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
I haven't examined the schematic in enough detail to quite convince
myself for sure the board will work without the RFSH signal, but that would
affect the writing/retention.
I'm a bit confused.. all DRAMs need a refresh, and the doc for this board
is pretty explicit that it needs "the correct" (ugh!) phase of the clock
signal "on pins 24 & 25". Why would you think the board doesn't
require
such a signal, that it has its own on-board refresh hardware? FWIW, there's
no crystal on-board to control an osc. to that level of precision.
To start in on board-level debugging, one thing
to check: if the board
is enabled and a valid address for the board is on the bus, then U4 pin 8
should be high.
Hey cool, that's the kind of info I need to keep me going. I'll take a
look at that in a bit.. or, take a look at that bit in a while or
something.
So here's a question or two. First off, how do you pronounce a letter
designation with a line over it - like the outputs of a flip-flop are Q and
(Q with overline). Do you say "Q high" or "Q prime".. "Q
complement" or
what? What about when a named signal such as CLOC or PWR has an overline?
Do you pronounce it "CLOC active high" or something?
(Does that line actually mean "active high"? - that's what I've
surmised..)
Finally, on the CPU board, pin 49 supplies the CLOC signal.. but it's
actually pins 25 & 24 that the DRAM card look to for +its+ clock signal.
Those pins are marked with what looks like a ?-1 and ?-2 (Greek Phi),
respectively. Is that actually a 'phi', and if so, what does it mean - what
are those signals, if not clock signals? And how do you pronounce them? It
could be a slashed-zero, too... "?".
(Generally Theta (?) is used to denote a phase / angular relationship or
quantity. it looks kinda like phi, but it's not.)
As for my trainer, or "chip tester" as I call it.. the only bad parts are
the +/-15 (var.) supplies. IIRC, the outputs are just the wipers of 1/4W
200R pots. Need to look at that again, and maybe it's time to install some
low-dropout linear regs ala LT1084 in there. Get some kind of stability and
over-current protection - when I received it, one of those pots was smoked.