Toby Thain <toby at telegraphics.com.au> wrote:
I think Jon is probably on to something.
You can check out the delays in my PIO bit-banging code here:
I tested it on a few drives & spent a lot of quality time with the
spec...of course I can't guarantee it would work for your specific
drive, but it might give you a clue where a delay is missing.
I think that what goes wrong in my code is the pure reading/writing
stuff since the IDENTIFY command works without any problem. So I
checked checked your ASM code for the PIC specific for that purpose.
From what I see in "ide_lbacmd" in ide.asm, you wait for BSY and DRQ
to get low, via "ide_devselect", then issue the drive+head register,
wait again for BSY and DRQ still in "ide_devselect" . Then, back in
"ide_lbacmd" you issue the other sector/cyl/head registers. Right
after that you issue the command to execute without any further
Now is the point where I get the error bit - so how the data is read
is probably not important here.
I'll tra to "redo" your code tonight, but beside that you issue the
drive+head first and I do just before I issue the command, I don't
see a big difference here.
I wonder if I could query the drive for the sector/cyl/head data it
works with to see if they where recieved correctly. I guess it just
gets invalid data for at least one of this so it response with ERR
for any read or write command because of "invalid addressing" (I
Do you know if there is a way to find out what sector/cyl/head the
drive tried to process the command?