8085 IO ports

On 01/14/2017 08:18 PM, dwight wrote: And maybe waiting for a interrupt? That's what I di when I'm building simple 8085 that interrupt driven. Let it loop doing repetitive stuff if anything, an example is the old days refreshing Dram. Then use RSTx.5 to force it into a active do something mode and when done back to the loop. A current project for myself has the 8085 runnign a simple multitasking OS and the loop runs through the task table and every task retruns to the loop. Interrupts are real time events or priority events that need out of sequence attention. The 8085 makes that fairly simple. I'd bet the Executel is doing that, refershing display and scanning for events with some interrupt driven for out of sequence response. Correct. IO/m will only stay high for an IO cycle for all memory cycles it goes low (instruction fetch, execute plus memory read or writes ). IO/m (there is a bar over the m) also goes high during a RST 5.5, 6.5, 7.5 and Trap if interrupts are enabled along with INTR. It could be you have a chip with a blown input (stuck low).. However doing that test is rather inconclusive as there is so much other state activity to track. Note during IO the a0-7 is mirrored to A8-15. Hummm... 4116 dram, that means you have external refresh logic or they are going cheap and doing refersh on a interrupt (or maybe) timed loop. A real schematic is likely a great aid too. Allison