17 Nov
2011
17 Nov
'11
9:37 a.m.
On Thu, 17 Nov 2011, Al Kossow wrote:
Date: Thu, 17 Nov 2011 08:47:46 -0800
From: Al Kossow <aek at bitsavers.org>
Reply-To: "General Discussion: On-Topic and Off-Topic Posts"
<cctalk at classiccmp.org>
To: cctalk at classiccmp.org
Subject: Re: on FPGA simulation
On 11/16/11 6:55 PM, Eric Smith wrote:
Well not for signals as such but a Flancter is good for cross domain status
flags
Peter Wallace
Note that everything in the FPGA doesn't have
to operate on the same clock.
You can have multiple clock domains.
Is there anything higher-level/better for describing an cross-domain signal
beyond specifying that it go through a
dual-rank synchronizer?