17 Nov
2011
17 Nov
'11
8:47 a.m.
On 11/16/11 6:55 PM, Eric Smith wrote:
Note that everything in the FPGA doesn't have to
operate on the same clock. You can have multiple clock domains.
Is there anything higher-level/better for describing an cross-domain signal beyond
specifying that it go through a
dual-rank synchronizer?