on FPGA simulation

On Nov 16, 2011, at 3:47 PM, Chuck Guzis wrote: Well, yeah, they'll complain, but that doesn't mean they won't build it. They're just confused because for the most part, they're built to expect synchronous designs and figure you're doing something wrong if they can't figure out a clock (and, honestly, for 99% of the designs out there, they're right; most people who are new to FPGAs don't understand what they're doing and develop things wrong and end up leaving out the clock or similar). The CPLD tools tend not to be as bitchy about it, mostly because registers are relatively scarce in CPLDs and so the converse is true; if you're using lots and lots of clocked registers, you're probably not using the right device for the job. My biggest pet peeve about FPGA design tools is the warnings they put out. You generally can't tell it "hey, this module is parameterized and generic so in this instance I'm not using this output", so anything you make properly generically will end up burying the real, important warnings in a sea of noise. You can't even use vendor IP (I'm especially thinking of memory controllers) without generating over 100 warnings, which drives me NUTS. I don't like combing through my synthesis report to see which of 800 messages is important. - Dave