2 Jan
2009
2 Jan
'09
11:31 p.m.
Jim Battle wrote:
Jules Richardson wrote:
>
> Someone asked this over on the Sinclair group a short while ago, but I
> suddenly thought that someone here might know...
>
> Basically they were wondering what the internals of the Z80's
> instruction fetch were, given that some instructions are multiple
> bytes in length, but there's only a single-byte instruction register.
...
Rodnay Zaks had a fat Z80 book that went into quite
some detail of the
timing of the bus and mentioned a hidden "W" register, but I don't
recall what that was for -- holding a byte temporarily during some
do-si-do. I have the book but it is buried in the garage.
I have a Radio Shack publication "How To Program the Z80" by Rodnay Zaks, but
I'm 99% sure
it was sold previously via a standard publishing house and RS just had this version with
the different jacket.
Chapter 2 is the one you want. It goes through an instruction fetch and exectute sequence
clock phase by clock phase, and shows what happens each cycle.
T1: PC Out (HL gated on to address bus)
T2: PC=PC+1
T3: INST into IR, start decoding
T4: decode and execute (minimum case -- more cycles needed often)
He steps through these instructions
LD D,C
(explains that it needs 5 T states instead of four, because the register file is not dual
ported)
ADD A,r
he shows that an extra clock phase is introduced that slows down the execution of this
instruction, but really is used to start the fetch of the next instruction -- there is a
slight amount of fetch/execute overlap.
Figure 2.27 shows the bus activity and some internal bus activity for each 8080
instruction, cycle by cycle, lifted from an intel data book, so somewhere this information
was already public.
ADD A,(HL)
A more complicated example.
ADD A,(nnnn)
This shows the use of two hidden registers, W and Z -- they are analogous to another 16b
BC pair. These hold the immediate 16b address fetch, since the CPU needs to hold a 16b
value for the duration of that instruction that isn't retained afterward.