2 Jan
2009
2 Jan
'09
12:30 p.m.
Someone asked this over on the Sinclair group a short while ago, but I
suddenly thought that someone here might know...
Basically they were wondering what the internals of the Z80's instruction
fetch were, given that some instructions are multiple bytes in length, but
there's only a single-byte instruction register.
I theorised that control in the Z80 is all just a state machine, so multiple
instruction bytes presumably advance things to a new state (and what's left in
the IR during execution is just one byte from a multi-byte instruction) - but
it sounds like the OP was wondering if anyone knew the exact mechanism
(basically, has the design of the state machine ever been documented anywhere).
(Given that I'm on a 'homebrew CPU' trip right now, I'm rather curious,
too :-)
Quite possibly this level of detail's never been made publicly available, but
I figure someone here may have had close involvement with Zilog and know more.
Online resources cover the overall internal architecture, but just 'black box'
the control logic section (including the IR).
cheers
Jules
2 Jan
2 Jan
5:44 p.m.
On Fri, 2 Jan 2009, Jules Richardson wrote:
Someone asked this over on the Sinclair group a short
while ago, but I
suddenly thought that someone here might know...
Basically they were wondering what the internals of the Z80's instruction
fetch were, given that some instructions are multiple bytes in length, but
there's only a single-byte instruction register.
I theorised that control in the Z80 is all just a state machine, so multiple
instruction bytes presumably advance things to a new state (and what's left
in the IR during execution is just one byte from a multi-byte instruction) -
but it sounds like the OP was wondering if anyone knew the exact mechanism
(basically, has the design of the state machine ever been documented
anywhere).
Wasn't the Z80 a microcoded design?
--
3 Jan
3 Jan
6:55 a.m.
Steven Hirsch wrote:
...
Wasn't the Z80 a microcoded design?
no! the same guy who did the 8080 layout, masatoshi shima, did the z80 layout. He also
did the z8000 layout, which was much more complex, but was also not microcode, just random
logic.
I just found this while googling to support my answer, but i've only skimmed it - a 47
page interview with Shima, done by the CHM:
http://www.ieee.org/portal/cms_docs_iportals/iportals/aboutus/history_cente…
7:34 a.m.
Jim Battle wrote:
Steven Hirsch wrote:
...
Having read more, Shima did the logic design on the 4004, 8080 and z80, and did the layout
on the 8080. I've also heard he led the layout for the z8000.
It is quite interesting to compare Shima's version of 4004 history and Federico
Fagin's.
In Fagin's version, he virtually did everything himself, with a bit of help from
Shima.
In Shima's version of events, he and Ted Hoff did all the spec work and design down to
the
transistor level, and Fagin was the guy who knew the process and layout end of things.
Fagin believes Intel has tried to erase his contribution to the 4004 and later intel
processors in retaliation against his starting Zilog, yet Shima also went to zilog and
isn't erased, and obviously Fagin and Shima had a good enough relationship to work
together at zilog for years, and Shima gives Fagin credit only for the back end of the
4004 design flow.
Wasn't the Z80 a microcoded design?
no! the same guy who did the 8080 layout, masatoshi shima, did the z80
layout. He also did the z8000 layout, which was much more complex, but
was also not microcode, just random logic.
I just found this while googling to support my answer, but i've only
skimmed it - a 47 page interview with Shima, done by the CHM:
http://www.ieee.org/portal/cms_docs_iportals/iportals/aboutus/history_cente…
8:31 a.m.
Jim Battle wrote:
Jim Battle wrote:
crap -- ... he also did the layout on the 8080 and z80, and led the layout for the
z8000.
Steven Hirsch wrote:
...
Having read more, Shima did the logic design on the 4004, 8080 and z80,
and did the layout on the 8080. I've also heard he led the layout for
the z8000.
Wasn't the Z80 a microcoded design?
no! the same guy who did the 8080 layout, masatoshi shima, did the
z80 layout. He also did the z8000 layout, which was much more
complex, but was also not microcode, just random logic.
I just found this while googling to support my answer, but i've only
skimmed it - a 47 page interview with Shima, done by the CHM:
http://www.ieee.org/portal/cms_docs_iportals/iportals/aboutus/history_cente…
2 Jan
2 Jan
8:09 p.m.
Jules Richardson wrote:
Someone asked this over on the Sinclair group a short while ago, but I
suddenly thought that someone here might know...
Basically they were wondering what the internals of the Z80's
instruction fetch were, given that some instructions are multiple bytes
in length, but there's only a single-byte instruction register.
I theorised that control in the Z80 is all just a state machine, so
multiple instruction bytes presumably advance things to a new state (and
what's left in the IR during execution is just one byte from a
multi-byte instruction) - but it sounds like the OP was wondering if
anyone knew the exact mechanism (basically, has the design of the state
machine ever been documented anywhere).
(Given that I'm on a 'homebrew CPU' trip right now, I'm rather curious,
too :-)
Quite possibly this level of detail's never been made publicly
available, but I figure someone here may have had close involvement with
Zilog and know more. Online resources cover the overall internal
architecture, but just 'black box' the control logic section (including
the IR).
Rodnay Zaks had a fat Z80 book that went into quite some detail of the timing of the bus
and mentioned a hidden "W" register, but I don't recall what that was for --
holding a
byte temporarily during some do-si-do. I have the book but it is buried in the garage.
I have no doubt prefix bytes, (CB, ED, DD, FD) just set a flop that modify the
interpretation of subsequent fetches -- that is more economical than storing the entire
byte (or two bytes in some cases). Immediates and IX/IY offsets just go right to the
latch in front of the ALU.
I'll try and find the book.
8:31 p.m.
Jim Battle wrote:
Jules Richardson wrote:
>
> Someone asked this over on the Sinclair group a short while ago, but I
> suddenly thought that someone here might know...
>
> Basically they were wondering what the internals of the Z80's
> instruction fetch were, given that some instructions are multiple
> bytes in length, but there's only a single-byte instruction register.
...
Rodnay Zaks had a fat Z80 book that went into quite
some detail of the
timing of the bus and mentioned a hidden "W" register, but I don't
recall what that was for -- holding a byte temporarily during some
do-si-do. I have the book but it is buried in the garage.
I have a Radio Shack publication "How To Program the Z80" by Rodnay Zaks, but
I'm 99% sure
it was sold previously via a standard publishing house and RS just had this version with
the different jacket.
Chapter 2 is the one you want. It goes through an instruction fetch and exectute sequence
clock phase by clock phase, and shows what happens each cycle.
T1: PC Out (HL gated on to address bus)
T2: PC=PC+1
T3: INST into IR, start decoding
T4: decode and execute (minimum case -- more cycles needed often)
He steps through these instructions
LD D,C
(explains that it needs 5 T states instead of four, because the register file is not dual
ported)
ADD A,r
he shows that an extra clock phase is introduced that slows down the execution of this
instruction, but really is used to start the fetch of the next instruction -- there is a
slight amount of fetch/execute overlap.
Figure 2.27 shows the bus activity and some internal bus activity for each 8080
instruction, cycle by cycle, lifted from an intel data book, so somewhere this information
was already public.
ADD A,(HL)
A more complicated example.
ADD A,(nnnn)
This shows the use of two hidden registers, W and Z -- they are analogous to another 16b
BC pair. These hold the immediate 16b address fetch, since the CPU needs to hold a 16b
value for the duration of that instruction that isn't retained afterward.
3 Jan
3 Jan
6:46 a.m.
Jim Battle wrote:
I have a Radio Shack publication "How To Program
the Z80" by Rodnay
Zaks, but I'm 99% sure it was sold previously via a standard publishing
house and RS just had this version with the different jacket.
Yes, that is correct. I have both versions! The original was called
"Programming the Z80" and was sold by Sybex along with "Programming
the 6502" and "Programming the 6809".
--
John Honniball
coredump at gifford.co.uk
6 Jan
6 Jan
12:14 p.m.
bfranchuk at jetnet.ab.ca wrote:
John Honniball wrote:
Thank you for reminding me about that one! I found a copy, and
it arrived in the post this morning. Now that I've seen the cover,
I recall that a friend had one in about 1985, to build a Z8000
machine for his final-year university project.
--
John Honniball
coredump at gifford.co.uk
Yes, that is correct. I have both versions! The
original was called
"Programming the Z80" and was sold by Sybex along with "Programming
the 6502" and "Programming the 6809".
And programming the Z8000 ...
4 Jan
4 Jan
9:32 a.m.
Jim Battle wrote:
This shows the use of two hidden registers, W and Z --
they are
analogous to another 16b BC pair. These hold the immediate 16b address
fetch, since the CPU needs to hold a 16b value for the duration of that
instruction that isn't retained afterward.
Yes, I think I've seen somewhere that W and Z were used to assemble a
temporary 16b address - however, that's a different kettle of fish; this chap
was wondering how multi-byte instructions (i.e. where the opcode itself is
longer than a single byte) get decoded.
It does seem logical (to both of us, anyway) that it's just a set of
flip-flops set by the prefix bytes to indicate different states - but so far
it seems that this isn't actually documented anywhere (presumably because it
doesn't *need* to be as far as anyone using the CPU is concerned)
I have the Zaks 'fat book' (and the Zilog A4-sized reference publication) but
unfortunately they're stuck in storage :-(
cheers
Jules
10:33 a.m.
On 4 Jan 2009 at 11:32, Jules Richardson wrote:
It does seem logical (to both of us, anyway) that
it's just a set of
flip-flops set by the prefix bytes to indicate different states - but so far
it seems that this isn't actually documented anywhere (presumably because it
doesn't *need* to be as far as anyone using the CPU is concerned)
From an operational standpoint concerning DD and FD, it
makes sense.
All of those "undocumented" instructions involving half of
IX or IY
are just normal DE and HL-involved instructions with a prefix byte.
But the CB and ED opcodes are radically different from their single-
byte cousins and I suspect that a different mechanism is at play
here. Perhaps they switch to a different section of the decoding
PLA.
Cheers,
Chuck
6 Jan
6 Jan
4:09 a.m.
On Fri, Jan 02, 2009 at 10:09:36PM -0600, Jim Battle wrote:
Rodnay Zaks had a fat Z80 book that went into quite
some detail of the
timing of the bus and mentioned a hidden "W" register, but I don't recall
what that was for -- holding a byte temporarily during some do-si-do. I
have the book but it is buried in the garage.
The book is Programming The Z80, now sadly out of print but commonly
available second-hand. It's a very good book on assembler programming
in general as well as being an excellent Z80 reference - although note
that it ignores *all* the "undocumented" instructions. He also mentions
a hidden Z register, but never mentions what W and Z are used for.
In my emulator, I use W whenever doing things with (HL) and Z in the CP
and CPI instructions. In both cases I could have used a temporary
variable instead, but I chose early on to implement them as registers to
keep the internal API a bit more consistent if I found myself using
them.
Source code, for those who care:
http://drhyde.cvs.sourceforge.net/viewvc/drhyde/perlmodules/CPU-Emulator-Z8…
--
David Cantrell | Enforcer, South London Linguistic Massive
Perl: the only language that makes Welsh look acceptable
3:56 a.m.
On Fri, Jan 02, 2009 at 02:30:25PM -0600, Jules Richardson wrote:
Basically they were wondering what the internals of
the Z80's instruction
fetch were, given that some instructions are multiple bytes in length, but
there's only a single-byte instruction register.
Speaking from memory (fairly recent memory as it happens, from writing
an emulator) there are two types of multi-byte instruction:
1. one byte instruction + data (eg a value to load into a register)
2. prefix byte(s) + one byte instruction (+ data for some instructions)
The prefix bytes either:
1. effectively swap the HL and IX or IY register
(the DD and FD prefixes)
2. change to a different instruction set
(the CB and ED prefixes)
3. are insane and look suspiciously like the state machine doing a
fandango (the DD CB and FD CB prefixes). AFAIK Zilog never documented
any of these.
That last case includes instructions like "attempt to reset bit 3 of the
byte at (IX+42) and also put the result in register B, even if the new
byte cannot be written at the said address".
See this excellent page on how to decode an instruction byte,
specifically these sections for the various prefix bytes:
http://www.z80.info/decoding.htm#cb
http://www.z80.info/decoding.htm#ed
http://www.z80.info/decoding.htm#dd
--
David Cantrell | Godless Liberal Elitist
Us Germans take our humour very seriously
-- German cultural attache talking to the Today Programme,
about the German supposed lack of a sense of humour, 29 Aug 2001
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participants (7)
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bfranchuk＠jetnet.ab.ca -
cclist＠sydex.com -
coredump＠gifford.co.uk -
david＠cantrell.org.uk -
frustum＠pacbell.net -
jules.richardson99＠gmail.com -
snhirsch＠gmail.com