DEC F-11 Pinout

On Wed, Jul 31, 2013 at 02:40:32AM -0400, Paul Birkel wrote: I could have this entirely wrong, but there's stuff in RT-11 which puts NOPs after instructions that might cause bus timeouts, and my understanding is that it's because the T11 doesn't innately know about timeouts so the Falcon's Q-bus interface fakes them by doing a hardware interrupt through vector 4 (at prio=7 I assume?), which isn't guaranteed to take place before the next instruction fetch. Which means it breaks the usual autosize code: tst @#devcsr ;touch device (TST clears C) bcs 10$ ;isn't there ... ;is there (with vector 4 pointing at something like "bis #1,2(sp) / rti") ... which works on *every* other PDP-11 model. So it's annoying to have to special-case your code for this one CPU model, and it's not even some ancient kludge from the dark ages (which would be understandable), it's a fancy 1980s LSI chip made when they should have known better. All assuming I'm right about the behavior, which maybe I'm not -- I've only barely played with a Falcon, and it was many years ago. John Wilson D Bit